TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 336

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

(11) Hardware flow control
serial data flow by using the UxRTSn output and UxCTSn input signals.
hardware flow control.
RTS flow control
CTS flow control
levels. When RTS flow control is enabled, the UxRTSn is asserted until the receive
FIFO is filled up to the watermark level.
UxRTSn signal is deasserted, indicating that there is no more room to receive.
and it is filled to less than the watermark level.
before transmitting. If the UxCTSn signal is asserted, it transmits the byte,
otherwise transmission does not occur.
is not empty. If the transmit FIFO is empty, no data is transmitted even when the
UxCTSn signal is asserted.
data transmission is completed before stopping.
The hardware flow control feature is fully selectable, and enables you to control the
Figure 3.13.5 shows how the two devices can communicate with each other using
Flow Control
Flow Control
The RTS flow control logic is linked to the programmable receive FIFO watermark
When the amount of data stored in the receive FIFO exceeds watermark level, the
The UxRTSn signal is reasserted when data has been read out of the receive FIFO
Even if RTS flow control is disabled, communication can be enabled.
If CTS flow control is enabled, then the transmitter checks the UxCTSn signal
The data transmission continues while UxCTSn is asserted and the transmit FIFO
If the UxCTSn signal is deasserted while CTS flow control is enabled, the current
Even if CTS flow control is disabled, communication can be enabled.
Rx FIFO
UART A
Tx FIFO
and
and
Figure 3.13.5 Hardware Flow Control
UxRTSn
UxCTSn
TMPA901CM- 335
UxRTSn
UxCTSn
Flow Control
Flow Control
UART B
Rx FIFO
Tx FIFO
and
and
TMPA901CM
2010-07-29