TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 534

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:7]
[6:0]
[31:16]
[15:0]
Bit
Bit
[Description]
[Description]
size[6:0]
data[15:0]
a. <size[6:0]>
a. <data[15:0]>
Symbol
Symbol
Indicates the number of valid data bytes stored in EP0_FIFO.
Used for accessing data from PVCI-I/F to EP0.
For the method of accessing this register, see section 3.16.3.5 “(1) Control-RD transfer”,
and section 3.16.3.5 “(3) Control-WR transfer (with DATA-Stage).”
It will be cleared to when the Setup-Token is received.
The data stored in this register will be cleared when the request is received (when the
INT_SETUP interrupt is asserted).
3.
4.
Bit
Bit
UD2EP0DSZ (EP0_Datasize register)
UD2EP0FIFO (EP0_FIFO register)
RO
R/W
Type
Type
Undefined
0y0000000,
(-)(-)(-)(-)(-)(-)(-)
Undefined
Undefined
Reset
Value
TMPA901CM- 533
Reset
Value
Read as undefined. Write as zero.
Used for accessing data from PVCI-I/F to EP0.
Read as undefined.
Indicates the number of valid data bytes stored in EP0_FIFO.
It will be cleared to when the Setup-Token is received.
Description
Address = (0xF440_0000) + (0x0238)
Address = (0xF440_0000) + (0x023C)
Description
TMPA901CM
2010-07-29