TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 50

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

from the XT1 and XT2 pins is defined as f
defined as clock f
clock obtained by dividing f
peripheral IPs connected to the APB bus, a clock obtained by dividing f
as f
memory controller, and as a SRAM/NORF clock, f
by 2 can be selected (Please refer to MPMC section).
Clock frequency input from the X1 and X2 pins is defined as f
Also, two types of clock, for DRAM and for SRAM/NORF respectively, are input in the
PCLK
(Signal name: PCLK)
FCLK
for the CPU core. For peripheral IPs connected to the AHB bus, a
.
FCLK
TMPA901CM- 49
by 2 is defined as f
S
, and the clock selected in SYSCR1<GEAR2:0> is
HCLK
or a clock obtained by dividing f
HCLK
(Signal name: HCLK). For
OSCH
, clock frequency input
FCLK
by 2 is defined
TMPA901CM
2010-07-29
HCLK