TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 611
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TMPA901CMXBG
Manufacturer Part Number
TMPA901CMXBG
Description
Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
Manufacturer
Toshiba
Datasheet
1.TMPA901CMXBG.pdf
(858 pages)
Specifications of TMPA901CMXBG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
-
Rom Type
ROMless
Ram (kbytes)
32
Number Of Pins
177
Package
BGA
Vcc
3V
Tft Lcd Controller
Y
Touchscreen Controller
Y
Usb Host Fs With Phy
Y
Usb Device Hs With Phy
Y
Sd Host Controller
-
Cmos Image Sensor Interface
-
I2s
1
Ssp (ch) Spi
1
I2mc/sio (ch)
1
Uart/sio (ch)
2
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
8
10-bit Ad Converter
4
12-bit Da Converter
-
16-bit Timer / Counter
6
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
Y
Low-power Modes
Y
Lead Free Status / Rohs Status
Details
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Part Number
Manufacturer
Quantity
Price
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Horizontal
sync signal
LCLLP
Panel clock
LCLCP
Panel data
LCD[15:0]
LCLAC
LCLLE
Signal name
(Horizontal sync
Note: For CPL, divide PPL by 1 (TFT), 4 or 8 (monochrome STN), or (2 + 2/3) (color STN) to set the division value.
(example: HSW = 6, HBP = 10) prevents data from being corrupted even when PCD = 4
(minimum value).
LCDTiming2<IPC> = 0, LCDTiming2<IOE> = 0):
pulse)
HSW
There is a restriction on the operation mode used.
Depending on usage conditions, setting enough time before the start point of line
The figure below shows an example of operation mode settings (LCDTiming2<IHS> = 1,
Limitations on horizontal timing
Horizontal non-data area
minimum values are HSW = 2, HBP = 2.
STN single panel mode:
STN Dual panel mode:
HSW = 3
HBP = 5
HFP = 5
Panel clock divisor (PCD) = 1(HCLK/3)
HSW = 3
HBP = 5
HFP = 5
PCD = 5(HCLK/7)
(Horizontal back
Figure 3.18.3 Basic operation of horizontal control
porch)
HBP
(Number of valid data pixels)
TMPA901CM- 610
(Number of clocks per line)
16*(PPL+1)
CPL
(Delay of CLLE)
(Horizontal front porch)
Horizontal non-data area
LED
HFP
4-HCLK width
TMPA901CM
2010-07-29
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