TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 523

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

k. < i_ep0>
l.
m. <i_rx_data0>
n. <i_status>
o. <i_status_nak>
p. <i_status_nak>
< i_sof>
This will be set to 1 when the SOF-token is received or after 1 frame-time was counted in
the create_sof mode.
This will be set to 1 when Zero-Length data is received. (EPs to which you wish to output
the flag can be selected using INT_EP_MASK register). Writing 1 to this bit will make
each bit of INT_RX_DATA0 register cleared to 0. This will not be set to 1 when
Zero-Length data is received in the STATUS-Stage of Control-RD transfers.
This will be set to 1 when the STATUS-Stage has successfully finished in Control
transfers at EP0. (This will be set to 1 when Zero-Length data is received in the
STATUS-Stage and successfully finished in Control-RD transfers, and when Zero-Length
data is transmitted in the STATUS-Stage and successfully finished in Control-WR
transfers.)
This will be set to 1 when the packet of STATUS-Stage is received in the Control-RD
transfers at EP0. When this bit was set which means the DATA-Stage has finished, set
the “Setup-Fin” command by the Command register to make the stage of UDC2 proceed to
the STATUS-Stage. When receiving the data having the size of an integral multiple of
MaxPacketSize (64 bytes: High-Speed) in the DATA-Stage of Control-WR transfers,
Zero-Length data may be received to indicate the end of the DATA-Stage. After that, as
the end of the DATA-Stage can be recognized by this i_status_nak when receiving the
In-token in the STATUS-Stage, make UDC2 proceed to the STATUS-Stage.
This will be set to 1 when the Setup-Token was received in Control transfers at EP0.
This will be set to 1 when the transfer to EP0 has successfully finished.
TMPA901CM- 522
TMPA901CM
2010-07-29