TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 564

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

(2)
(UDC2-Output)
xcvr_select
(UDC2-Output)
term_select
(UDC2-Output)
When Operating in FS Mode after Reset
DDP/DDM
T0: Reset start
T1: Reset recognition (more than 2.5 µs after T0)
T2: Device Chirp-K complete (more than 1.0 ms after T1)
T3: FS operation start (1.0 ms to 2.5 ms after T2)
T4: Reset end (more than 10 ms after T0)
usb_reset
When UDC2 detects SE0 for more than approximately 68 μs after T0, it recognizes the
reset from the host and drives usb_reset “H”. At the same time, UTMI starts the device
Chirp-K operation.
When the host supports FS mode, the host chirp-KJ operation is not performed. If no host
Chirp-KJ is detected in approximately 2 ms after T2, UDC2 initiates FS mode. At this
point, usb_reset is driven “L”. The period in which usb_reset remains “H” is
approximately 3.5 ms.
When SE0 from the host finishes and the device enters an idle state, it indicates the end of
reset operation. The reset period from the host lasts a minimum of 10 ms.
Upon recognizing SE0 from the host, UDC2 starts counting to recognize the reset.
UDC2 completes the device Chirp-K operation approximately 1.5 ms after T1.
time
Figure 3.16.28 Reset operation timing (FS mode after Chirp)
J
(H)
T0
SE0
T1
TMPA901CM- 563
Device
Chirp-K
T2
T3
SE0
TMPA901CM
2010-07-29
T4
J