TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 619

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:5]
[4]
[3]
[2]
[1]
[0]
Bit
7.
corresponding values in the original interrupt LCDRIS bit to the LCDMIS register.
MBERRINTRENB
VCOMPINTRENB
LNBUINTRENB
FUFINTRENB
LCDIMSC is the interrupt enable register. Setting the bits in this register passes the
LCDIMSC (Interrupt Mask Set/Clear Register)
Symbol
Bit
R/W
R/W
R/W
R/W
Type
Undefined
0y0
0y0
0y0
0y0
Undefined
TMPA901CM- 618
Reset
Value
Read as undefined. Write as zero.
AHB master error interrupt enable
0y0: Disable
0y1: Enable
Vertical sync. interrupt enable
0y0: Disable
0y1: Enable
Next base address update interrupt enable
0y0: Disable
0y1: Enable
FIFO underflow interrupt enable
0y0: Disable
0y1: Enable
Read as undefined. Write as zero.
Description
Address
(0xF420_0000) + (0x0018)
TMPA901CM
2010-07-29