TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 37

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.2.12
TMPA901CM.
This section describes the instructions supported by the JTAG controller cells of the
(1) EXTEST instruction
boundary scan register using the SAMPLE/PRELOAD instruction. If the boundary scan
register is not reset, indeterminate data will be transferred in the Update-DR state and bus
conflicts between ICs may occur. Figure 3.2.7 shows data flow when the EXTEST
instruction is selected.
1.
2.
3.
4.
5.
6.
7.
8.
Instructions Supported by the JTAG Controller Cells
instruction permits BSR cells at output pins to shift out test patterns in the Update-DR
state and those at input pins to capture test results in the Capture-DR state.
The EXTEST instruction is used for external interconnect tests. The EXTEST
Typically, before EXTEST is executed, the initialization pattern is shifted into the
The following steps describe the basic test procedure of the external interconnect test.
Repeat steps 6 to 8 for each test pattern.
Input
TDI
Reset the TAP controller to the Test-Logic-Reset state.
Load the instruction register with the SAMPLE/PRELOAD instruction. This causes
the boundary scan register to be connected between TDI and TDO.
Reset the boundary scan register by shifting certain data in.
Load the test pattern into the boundary scan register.
Load the instruction register with the EXTEST instruction.
Capture the data applied to the input pin into the boundary scan register.
Shift out the captured data while simultaneously shifting the next test pattern in.
Send out the test pattern in the boundary scan register at the output on the output pin.
Figure 3.2.7 Test Data Flow when the EXTEST Instruction is Selected
TMPA901CM- 36
Boundary scan path
Core logic
Output
TDO
TMPA901CM
2010-07-29