TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 406

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

SCL (bus)
SDA (bus)
I2C0DA
I2C0SR<AAS>
I2CINT0 interrupt request
3.14.6.11 Slave Address Match Detection Monitor
Figure 3.14.19 Arbitration lost operation (with internal flags associated with Master B)
Master
Master
is selected.
general call is received or the slave address sent from the master matches the slave address
set in I2C0AR<SA>, I2C0SR<AAS> is set to 1.
general call is received or the salve address sent from the master matches the slave address
set in I2C0AR<SA>, I2C0SR<AAS> remains 0.
detection, and I2C0SR<AAS> is set to 1 upon receipt of the first word of data. It is cleared
to 0 when data is written to or read from I2C0DBR.
A
B
I
Clearing I2C0CR1<NOACK> to 0 enables the slave address match detection. When a
Setting I2C0CR1<NOACK> to 1 disables the slave address match detection. Even if a
When the free data format is used (I2C0AR<ALS> = 1), it is not used as address match
I2C0SR<MST>
I2C0SR<TRX>
I2C0SR<AL>
2
C bus mode (I2C0AR<ALS> = 0) allows slave address match detection when slave mode
Internal SDA output
Internal SDA output
Internal SCL output
Internal SCL output
Access to I2C0DBR or
I2C0CR2
Start condition
Figure 3.14.20 Changes in the slave address match monitor
SA6
1
SA5
2
1
1
SA4
3
TMPA901CM- 405
2
2
Slave address + direction bit
SA3
3
3
4
Arbitration lost
Internal SDA output is fixed to high.
4
4
SA2
5
5
Clock output stopped from here
SA1
6
6
SA0
7
7
I2C0DBR write or read
R/
8
W
8
9
ACK output
9
TMPA901CM
2010-07-29