TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 366

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

26. UART0DMACR (UART0 DMA control register)
[31:3]
[2]
[1]
[0]
[Description]
a. <DMAONERR>
Bit
Note1: For example, if 19 characters have to be received and the watermark level is programmed to be four, then the
Note2: The bus width must be set to 8-bits, if you transfer the data of tranmit/ receive FIFO by using DMAC.
When this bit is set to 1, the DMA receive request output, UARTxRXDMASREQ or
UARTxRXDMABREQ, is disabled on assertion of a UART error interrupt.
DMA controller transfers four bursts of four characters and three single transfers to complete the stream.
DMAONERR
TXDMAE
RXDMAE
Symbol
Bit
R/W
R/W
R/W
Type
TMPA901CM- 365
0y0
0y0
0y0
Reset
Value
Read as undefined. Write as zero.
DMA on error
0y1: Available
0y0: Not available
Transmit FIFO DMA enable
0y0: Disable
0y1: Enable
Receive FFO DMA enable
0y0: Disable
0y1: Enable
Address
Description
(0xF200_0000) + (0x0048)
TMPA901CM
2010-07-29