TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 487

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

Master Write transfer sequence
Note: UDC2AB will assert the int_mw_set_add interrupt when the packet is received normally from the USB host
(4) Master Write transfer
with the mw_enable bit of DMAC Setting register disabled.
operations will be as follows:
The operation of Master Write transfers are discussed here. Master Write
1. Set Master Write Start Address and Master Write End Address registers.
2. Set the bits associated to the Master Write operation of DMAC Setting
3. UDC2AB makes a Master Write transfer to the data in the endpoint
4. Since the int_mw_end_add interrupt will be asserted when the writing
register and set 1 to the mw_enable bit.
received from the USB host.
ended to reach the Master Write End Address (with no timeout processed),
you should make necessary arrangement with the software. UDC2 will
return to 1 after receiving the correct packet.
TMPA901CM- 486
TMPA901CM
2010-07-29