TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 536

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:16]
[15]
[14]
[13:12]
[11:9]
[8]
[7]
[6:4]
[3:2]
[1:0]
Bit
pkt_mode
bus_sel
toggle[1:0]
status[2:0]
disable
dir
t_type[1:0]
num_mf[1:0]
Note 1: Setting for this register should be made when configuring the endpoint when Set_Configuration and
Note 2: Since the register structure is identical for EP1, EP2 and EP3, only EP1 is described here.
Symbol
2.
Bit
For EP1 which is fixed for IN transfers, dir can be set to "1" only.
For EP2 which is fixed for OUT transfers, dir can be set to "0" only.
For EP3 which is fixed for IN transfers, dir can be set to "1" only.
Set_Interface are received.
Addresses of registers for EP2 and EP3 can be confirmed in the register map.
Each EP depend on the produnct specification.
UD2EP1STS (EP1_Status register)
R/W
R/W
RO
RO
RO
R/W
R/W
R/W
Type
Undefined
0y0
0y0
0y0
0y0
Undefined
0y00
0y00
0y00
0y111
Reset
Value
TMPA901CM- 535
Read as undefined. Write as zero.
Select the packet mode of EP1.
0y0: Single mode
0y1: Dual mode
Select the bus to access to the FIFO of EP1.
0y0: Common bus access
0y1: Direct access
Indicates the present toggle value of EPx.
0y00: DATA0
0y10: DATA2
Indicates the present status of EP1. By issuing EP_Reset from
Command register, the status will be "Ready."
0y000: Ready
0y001: Reserved
0y010: Error
0y011: Stall
0y100-0y110: Reserved
0y111: Invalid
Indicates whether transfers are allowed for EP1.
0y0: Allowed
0y1: Not Allowed
Sets the direction of transfers for this endpoint.
0y0: OUT (Host-to-device)
0y1: IN (Device-to-host)
Read as undefined. Write as zero.
Sets the transfer mode for this endpoint.
0y00: Control
0y10: Bulk
When the Isochronous transfer is selected, set how many times
the transfer should be made in μ frames.
0y00: 1-transaction
0y10: 3-transaction
0y01: DATA1
0y11: MDATA
0y01: Isochronous
0y11: Interrupt
0y01: 2-transaction
0y11: Reserved
Description
Address = (0xF440_0000) + (0x0244)
TMPA901CM
2010-07-29