TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 546

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

Data flow on USB
cable
INT_STATUS _NAK
Register access
EP0_DATASET
INT_STATUS
INT_SETUP
Figure 3.16.22 Example of using the INT_STATUS_NAK flag in Control-RD transfers
INT_EP0
UDC2
1.
2.
Host
(4) Example of using the INT_STATUS_NAK flag
get asserted by receiving STATUS-Stage from the host before clearing the INT_SETUP
flag after it has been asserted, especially in High-Speed transfers. In case such
multiple interrupts should be avoided as much as possible, you can use a method to
mask the INT_STATUS_NAK flag for request having no DATA-Stage. In such case,
basically set 1 to “m_status_nak” of INT register, while 0 should be set only when
requests having DATA-Stage are received. (An example for Control-RD transfers is
provided below.)
After the INT_SETUP flag was asserted, clear the bit 0 (i_setup) of INT register. If the
bit 1 (i_status_nak) is set to 1, it should be also cleared.
Then, if the request was judged to have DATA-Stage by reading Setup-Data storage
registers, set the bit 9 (m_status_nak) of INT register to 0. Then issue the
“Setup_Received” command.
When the INT_STATUS_NAK flag was asserted, the device should also proceed to the
STATUS-Stage. Clear the bit 1 (i_status_nak) of INT register and then issue the
“Setup_Fin” command. Also, set 1 to the bit 9 (m_status_nak) of INT register in order
to get ready for subsequent transfers.
SETUP-Stage
DATA-Stage → STATUS-Stage
When processing requests without DATA-Stage, the INT_STATUS_NAK flag may
SETUP
SETUP-Stage
INT-Reg.
(8 bytes)
Read
DATA0
ACK
INT-Reg.
Write
Register Read (8 bytes)
Setup-Data storage
IN
INT-Reg.
NAK
Write
TMPA901CM- 545
Issue Setup_Received
IN
(MaxPacketSize byte)
Command
EP0_FIFO Write
NAK
IN
DATA-Stage（IN）
(Transmission
DATA1
INT-Reg.
data)
Read
ACK
(MaxPacketSize byte)
EP0_FIFO Write
INT-Reg.
Write
OUT
INT-Reg.
Read
(0 byte)
DATA1
NAK
INT-Reg.
Write
Issue Setup_Fin
OUT
Command
STATUS-Stage
TMPA901CM
(0 byte)
DATA1
2010-07-29
INT-Reg.
Read
ACK
INT-Reg.
Write