TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 416

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

• Serial frame (SP0FSS)
asserted during the entire transmission of the frame.
transmission of each frame. For this frame format, output data is transmitted on the rising
edge of SP0CLK, and input data is received on the falling edge.
• Microwire frame format
at half-duplex. In this mode, when a frame begins, an 8-bit control message is transmitted
to the slave. During this transmission, no incoming data is received by the SSP. After the
message has been sent, the slave decodes it and, after waiting one serial clock period after
the last bit of the 8-bit control message has been sent, responds with the requested data.
The returned data can be 4 to 16 bits in length, making the total frame length anywhere
from 13 to 25 bits.
For SPI and Microwire frame formats, the serial frame (SP0FSS) pin is active Low, and is
For SSI frame format, the SP0FSS pin is asserted for one bit rate period prior to the
The Microwire format uses a special master-slave messaging technique, which operates
The details of each frame format are described below.
SP0DO is put in the Hi-Z state whenever the SSP is idle. When data is written into the
transmit FIFO, the master pulses the SP0FSS line High for one SP0CLK period. The
transmit data is transferred from the transmit FIFO to the transmit serial shift
register. On the next rising edge of SP0CLK, the MSB of the 4 to 16-bit data frame is
shifted onto the SP0DO pin.
of SP0CLK. The received data is transferred from the serial shift register to the receive
FIFO on the first rising edge of SP0CLK after the LSB has been latched.
1) SSI frame format
In this mode, SP0CLK and SP0FSS are forced Low and the transmit data line
Likewise, the MSB of the received data is input to the SP0DI pin on the falling edge
SSI frame format (single transfer)
SP0CLK
SP0FSS
SP0DO
SP0DI
Hi-Z(Note1)
Hi-Z(Note2)
TMPA901CM- 415
MSB
MSB
4 to 16bit
LSB
LSB
Hi-Z(Note2)
Hi-Z(Note1)
TMPA901CM
2010-07-29