TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 384

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:8]
[7:0]
[31:8]
[7:0]
[Description]
a. <DB[7:0]>
Bit
Bit
Note:
Note: In receive mode, if data is written to I2C0DBR before the received data is read out, the received data will be
2.
aligned on the left side.
right side.
written to I2C0DBR<DB[7:1]> and the transfer direction is specified in I2C0DBR<DB[0]>
as follows:
dedicated transmit buffer in transmit mode and as a dedicated receive buffer in receive
mode. This register should be accessed on a transfer-by-transfer basis.
on the bus.
internal interrupt after the current transfer and initiates the next transfer.
These bits are used to store data for serial transfer.
When this module is a transmitter, the data to be transmitted is written into DB[7:0]
When this module is a receiver, the received data is stored into DB[7:0] aligned on the
When the master needs to transmit a slave address, the transfer target address is
0y0: Master (transmission)
0y1: Master (reception) ← Slave/transmission
When all the bits in the I2C0DBR register are written as 0, a general call can be sent out
In both transmission and reception modes, a write to the I2C0DBR register releases the
Although I2C0DBR is provided as a transmit/receive buffer, it should be used as a
I2C0DBR (I
corrupted.
This register is initialized only after a hardware reset. It is not initialized by a software reset. (The most recent
data is retained.)
DB[7:0]
DB[7:0]
Bit Symbol
Bit Symbol
2
C0 Data Buffer Register)
RO
WO
Type
Type
TMPA901CM- 383
Slave/reception
Undefined
0x00
Undefined
0x00
Reset
Reset
Value
Value
Read as undefined.
Read: Receive data is read (Note)
Read as undefined. Write as zero.
Write: Transmit data is written (Note)
Address
Address
Description
Description
(0xF007_0000) + (0x0004)
(0xF007_0000) + (0x0004)
TMPA901CM
2010-07-29