TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 466

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:0]
Bit
mwahbadr
[Description]
a. <mwahbadr>
Symbol
14. UDMWAHBADR (Master Write AHB Address register)
Displays the address where the transfer to the target device has completed in Master
Write transfer. This can be used in case a timeout interrupt has occurred or an error
occurred during the transfer process. This address is incremented at the point when the
data is set to the target device, while the data will reside inside the target device or during
the Master Write transfer process until the displayed address.
Bit
Write transfer (UDC2 to AHB).
Please note that the address to be saved is the word border even when accessing by byte.
Displays the address where the transfer to the target device has completed in Master
In some DMA transfers, accesses are made on a byte basis depending on the conditions.
RO
Type
0xFFFFFFFF
TMPA901CM- 465
Reset
Value
Master Write AHB address
Description
Address = (0xF440_0000) + (0x004C)
TMPA901CM
2010-07-29