TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 493

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.16.2.13 Suspend/Resume
Note: While UDC2AB originally has the function to assert the Wakeup signal, it is not supported for this LSI.
(1) Shift to the suspended state
(2) Resuming from suspended state
(3) Remote wakeup from suspended state
int_suspend_resume interrupt and the suspend_x bit of Power Detect Control register.
Since master transfers will not automatically stop in this circumstance, you should use
the aborting function of each master transfer to make forcible termination if needed. In
case PHY needs to be suspended (clock stop) after the necessary processes finished by
software, you can set the phy_suspend bit of Power Detect Control register to make
UDC2AB assert PHYSUSPEND_X which will put PHY in suspended state.
the int_suspend_resume interrupt and the suspend_x bit of Power Detect Control
register. (In case the wakeup_en bit of Power Control register is set to be enabled when
CLK_H is stopped, notification is made by the WAKEUP_X output signal.)
when resuming, controlling by software is not necessary unlike the case of suspending.
UDC2 supplied by PHY (CLK_U) are stopped. Setting the phy_remote_wkup bit of
Power Detect Control register to 1 in this state will make UDC2AB assert
udc2_wakeup to UDC2 while deasserting the PHYSUSPEND_X signal. When the clock
(CLK_U) output from PHY resumes after a certain period and the clock is supplied,
UDC2 will automatically start the resuming operation.
UDC2AB makes notification of detecting the suspended state of UDC2 by the
UDC2AB makes notification of detecting the resuming state from the USB host by
Since the suspend signal to PHY (PHYSUSPEND_X) is automatically deasserted
When resuming is recognized, make settings again for restarting master transfers.
When suspended, (in case PHY is in the suspended state) clocks for UDC2AB and
TMPA901CM- 492
TMPA901CM
2010-07-29