TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 598

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:4]
[3]
[2]
[1]
[0]
[Description]
Bit
a. <I2SRx_OVERFLOW_INT>, <I2SRx_UNDERFLOW_INT>, <I2STx_OVERFLOW_INT>,
Note: This register is corresponded when writing “0” to the corresponding bit of the interrupt mask register
15. I2SINT (I
<I2STx_UNDERFLOW_INT>
This register indicates the interrupt status of each interrupt source. To monitor the FIFO
error status by using each interrupt source, the corresponding bit of the interrupt mask
register (I2SINTMSK) must be cleared.
When an interrupt is generated from one of these sources, the interrupt controller
generates an I2SINT interrupt. The interrupt source can be identified by monitoring each
interrupt source bit of the I2SINT register.
Each bit of this register is cleared to 0 by writing 1.
(I2SINTMSK).
I2SRx_OVERFLOW_INT
I2SRx_UNDERFLOW_INT
I2STx_OVERFLOW_INT
I2STx_UNDERFLOW_INT
Bit Symbol
2
S Interrupt Register)
TMPA901CM- 597
R/W
R/W
R/W
R/W
Type
Undefined
0y0
0y0
0y0
0y0
Reset
Value
Rx FIFO overflow interrupt:
Read:
Write:
Rx FIFO underflow interrupt:
Read:
Write:
Tx FIFO overflow interrupt:
Read:
Write:
Tx FIFO underflow interrupt:
Read:
Write:
Read as undefined. Write as zero.
Address
Description
0y0: No interrupt
0y1: Interrupt generated
0y0: Invalid
0y1: Clear
0y0: No interrupt
0y1: Interrupt generated
0y0: Invalid
0y1: Clear
0y0: No interrupt
0y1: Interrupt generated
0y0: Invalid
0y1: Clear
0y0: No interrupt
0y1: Interrupt generated
0y0: Invalid
0y1: Clear
(0xF204_0000) + (0x0050)
TMPA901CM
2010-07-29