SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 101

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

19. Embedded Flash Controller (EFC)
19.1
19.2
19.2.1
6222F–ATARM–14-Jan-11
Overview
Functional Description
Embedded Flash Organization
The Embedded Flash Controller (EFC ) is a part of the Memory Controller and ensures the inter-
face of the Flash block with the 32-bit internal bus. It increases performance in Thumb Mode for
Code Fetch with its system of 32-bit buffers. It also manages the programming, erasing, locking
and unlocking sequences using a full set of commands.
The SAM7SE512 is equipped with two EFCs, EFC0 and EFC1. EFC1 does not feature the
Security bit and GPNVM bits. The Security bit and GPNVM bits embedded only on EFC0 apply
to the two blocks in the SAM7SE512.
The SAM7SE256/32 is equipped with one EFC (EFC0).
The Embedded Flash interfaces directly to the 32-bit internal bus. It is composed of several
interfaces:
The Embedded Flash size, the page size and the lock region organization are described in the
product definition section.
• One memory plane organized in several pages of the same size
• Two 32-bit read buffers used for code read optimization (see
• One write buffer that manages page programming. The write buffer size is equal to the page
• Several lock bits used to protect write and erase operations on lock regions. A lock region is
• Several general-purpose NVM bits. Each bit controls a specific feature in the device. Refer to
102).
size. This buffer is write-only and accessible all along the 1 MByte address space, so that
each word can be written to its final address (see
composed of several consecutive pages, and each lock region has its associated lock bit.
the product definition section to get the GPNVM assignment.
“Write Operations” on page
SAM7SE512/256/32
“Read Operations” on page
104).
101