SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 143

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 21-4.
21.6.5.3
6222F–ATARM–14-Jan-11
Mode
Attribute Memory
Common Memory
I/O Mode
Task File
Data Register
Control Register
Alternate Status Read
Drive Address
Standby Mode or
Address Space is not
assigned to CF
Read/Write Signals
CFCE1 and CFCE2 Truth Table
In I/O mode and True IDE mode, the CompactFlash logic drives the read and write command
signals of the SMC on CFIOR and CFIOW signals, while the CFOE and CFWE signals are deac-
tivated. Likewise, in common memory mode and attribute memory mode, the SMC signals are
driven on the CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated.
21-4 on page 144
presents the signal decoding.
Attribute memory mode, common memory mode and I/O mode are supported by setting the
address setup and hold time on the NCS4 (and/or NCS2) chip select to the appropriate values.
For details on these signal waveforms, please refer to the section: Setup and Hold Cycles of the
Static Memory Controller Section.
CFCE2
NUB
NUB
NUB
1
1
1
1
0
0
1
CFCE1
shows a schematic representation of this logic and
NLB
NLB
NLB
0
0
0
0
1
1
1
Alternate True IDE Mode
True IDE Mode
16 bits
16 bits
16 bits
16bits
DBW
8 bits
8 bits
8 bits
Don’t
8 bits
Don’t
Care
Care
Comment
Access to Even Byte on D[7:0]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Access to Odd Byte on D[7:0]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Access to Odd Byte on D[7:0]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[7:0]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[7:0]
Don’t Care
SAM7SE512/256/32
Table 21-5 on page 144
Don’t Care
SMC Access Mode
Byte Select
Byte Select
Don’t Care
Byte Select
Don’t Care
Don’t Care
Byte Select
Don’t Care
Don’t Care
Figure
143