SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 174

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

22.6.5
22.6.5.1
Figure 22-19. Read Access with Setup and Hold
174
A[22:0]
MCK
NRD
SAM7SE512/256/32
Setup and Hold Cycles
Read Access
The SMC allows some memory devices to be interfaced with different setup, hold and pulse
delays. These parameters are programmable and define the timing of each portion of the read
and write cycles. However, it is not possible to use this feature in early read protocol.
If an attempt is made to program the setup parameter as not equal to zero and the hold parame-
ter as equal to zero with WSEN = 0 (0 standard wait state), the SMC does not operate correctly.
If consecutive accesses are made to two different external memories and the second memory is
programmed with setup cycles, then no chip select change wait state is inserted (see
23 on page
When a data float wait state (t
memory bank is programmed with setup cycles, the SMC behaves as follows:
The read cycle can be divided into a setup, a pulse length and a hold. The setup parameter can
have a value between 1.5 and 7.5 clock cycles, the hold parameter between 0 and 7 clock
cycles and the pulse length between 1.5 and 128.5 clock cycles, by increments of one.
Figure 22-20. Read Access with Setup
• If the number of t
• If the number of the setup cycle is higher than the number of t
NRD Setup
cycles inserted is equal to 0 (see
0 (see
A[22:0]
Figure 22-25 on page
MCK
NRD
176).
DF
is higher or equal to the number of setup cycles, the number of setup
DF
) is programmed on the first memory bank and when the second
177).
NRD Setup
Figure 22-24 on page
Pulse Length
176).
Pulse Length
DF,
the number of t
NRD Hold
6222F–ATARM–14-Jan-11
DF
inserted is
Figure 22-