SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 206
SAM7SE256
Manufacturer Part Number
SAM7SE256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7SE256
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
48 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
88
Ext Interrupts
88
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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23.6.3
Figure 23-5. Read Burst with Boundary Row Access
206
D[31:0]
A[12:0]
SDWE
SDCS
SDCK
RAS
CAS
SAM7SE512/256/32
Border Management
col a
Row n
col b
Dna
col c
When the memory row boundary has been reached, an automatic page break is inserted. In this
case, the SDRAM controller generates a precharge command, activates the new row and ini-
tiates a read or write command. To comply with SDRAM timing parameters, an additional clock
cycle is inserted between the precharge/active (t
mand. This is described in
Dnb
col d
Dnc
Dnd
T
RP
= 3
Figure 23-5
Row m
below.
T
RCD
= 3
col a
RP
) command and the active/read (t
CAS = 3
col b
Dma
col c
Dmb
col d
Dmc
6222F–ATARM–14-Jan-11
col e
Dmd
RCD
Dme
) com-
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