SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 539

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6222F–ATARM–14-Jan-11
• the waveform duty cycle. This channel parameter is defined in the CDTY field of the
• the waveform polarity. At the beginning of the period, the signal can be at high or low level.
• the waveform alignment. The output waveform can be left or center aligned. Center aligned
(
------------------------------------------ -
(
----------------------------------------------------- -
will be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
PWM_CDTYx register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
This property is defined in the CPOL field of the PWM_CMRx register. By default the signal
starts by a low level.
waveforms can be used to generate non overlapped waveforms. This property is defined in
the CALG field of the PWM_CMRx register. The default mode is left aligned.
(
------------------------------- -
(
------------------------------------------ -
2
2
X
CRPD
duty cycle
duty cycle
×
×
×
MCK
X
CPRD
CPRD
MCK
MCK
×
MCK
×
CPRD
DIVA
)
×
DIVA
=
=
)
)
(
----------------------------------------------------------------------------------------------------------- -
(
----------------------------------------------------------------------------------------------------------------------------- -
period 1
or
(
period
)
(
---------------------------------------------- -
or
CRPD
(
----------------------------------------------------- -
2
–
×
⁄
MCK
×
CPRD
2
⁄
) 1
DIVAB
MCK
fchannel_x_clock
–
×
period
⁄
(
period
DIVB
)
fchannel_x_clock
)
⁄
2
)
×
CDTY
×
CDTY
)
SAM7SE512/256/32
) )
539