SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 200
SAM7SE256
Manufacturer Part Number
SAM7SE256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7SE256
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
48 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
88
Ext Interrupts
88
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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23.3
Table 23-1.
Note:
23.4
23.4.1
23.4.1.1
Table 23-2.
Table 23-3.
200
Name
SDCK
SDCKE
SDCS
BA[1:0]
RAS
CAS
SDWE
NBS[3:0]
A[12:0]
D[31:0]
2
7
2
7
Bk[1:0]
2
6
2
6
I/O Lines Description
1. SDCK is tied low after reset.
Application Example
SAM7SE512/256/32
Bk[1:0]
Bk[1:0]
2
5
2
5
Software Interface
32-bit Memory Data Bus Width
I/O Line Description
SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
Bk[1:0]
SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
Bk[1:0]
2
4
2
4
Description
SDRAM Clock
SDRAM Clock Enable
SDRAM Controller Chip Select
Bank Select Signals
Row Signal
Column Signal
SDRAM Write Enable
Data Mask Enable Signals
Address Bus
Data Bus
Bk[1:0]
Bk[1:0]
2
3
2
3
Bk[1:0]
2
2
2
2
The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to
the user.
by the user in correlation with the device structure. Various configurations are illustrated.
2
1
2
1
2
0
2
0
Row[11:0]
Table 23-2
1
9
1
9
Row[10:0]
Row[11:0]
1
8
1
8
Row[10:0]
Row[11:0]
1
7
1
7
Row[10:0]
to
Row[11:0]
Table 23-7
1
6
1
6
Row[10:0]
CPU Address Line
CPU Address Line
1
5
1
5
1
4
1
4
illustrate the SDRAM device memory mapping therefore seen
1
3
1
3
1
2
1
2
1
1
1
1
1
0
1
0
9
9
Column[10:0]
Column[10:0]
8
8
Column[9:0]
Column[9:0]
7
Column[8:0]
7
Column[8:0]
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
I/O
Column[7:0]
Column[7:0]
6
6
(1)
5
5
4
4
6222F–ATARM–14-Jan-11
3
3
Active Level
High
Low
Low
Low
Low
Low
2
2
1
1
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
0
0
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