SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 657

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

43.2.7.5
43.2.8
43.2.8.1
43.2.9
43.2.9.1
43.2.9.2
43.2.9.3
6222F–ATARM–14-Jan-11
Two Wire Interface (TWI)
Universal Synchronous Asynchronous Receiver Transmitter (USART)
TWI: Switching from Slave to Master Mode
USART: Two Characters Sent with Hardware Handshaking
USART: DCD is Active High Instead of Low
SSC: First RK Clock Cycle when Rk Outputs a Clock During Data Transfer
USART: CTS in Hardware Handshaking
At the end of the data, the RK pin is set in high impedance which might be seen as an unex-
pected clock cycle.
Enable the pull-up on RK pin.
When the SSC receiver is used with the following conditions:
The first clock cycle time generated by the RK pin is equal to MCK/(2 x (value +1)).
None.
When the TWI is set in slave mode and if a master write access is performed, the start event is
correctly generated but the SCL line is stuck at 1, so no transfer is possible.
Two software workarounds are possible:
When Hardware Handshaking is used and if CTS goes high near the end of the starting bit, a
character can be lost.
CTS must not go high during a time slot occurring between 2 Master Clock periods before the
starting bit and 16 Master Clock periods after the rising edge of the starting bit.
None.
When Hardware Handshaking is used and if CTS goes high during the TX of a character and if
the holding register (US_THR) is not empty, the content of the US_THR will also be transmitted.
Don’t use the PDC in transmit mode and do not fill US_THR before TXRDY is set at 1.
DCD signal is active at “High” level in USART block (Modem Mode).
DCD should be active at “Low” level.
• RX clock is divided clock (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0),
1. Perform a software reset before going to master mode (TWI must be reconfigured).
2. Perform a slave read access before switching to master mode.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
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