SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 354

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 32-7. Master Write with Multiple Data Byte
Figure 32-8. Master Write with One Byte Internal Address and Multiple Data Bytes
32.7.5
354
TXCOMP
TXCOMP
TXRDY
TXRDY
TWD
TWD
Write THR (Data n)
SAM7SE512/256/32
Master Receiver Mode
S
Write THR (Data n)
S
DADR
DADR
Figure 32-6. Master Write with One Data Byte
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data
has been received, the master sends an acknowledge condition to notify the slave that the data
has been received except for the last data, after the stop condition. See
RXRDY bit is set in the status register, a character has been received in the receive-holding reg-
ister (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
W
W
TXCOMP
A
TXRDY
TWD
IADR(7:0)
A
Write THR (DATA)
S
Write THR (Data n+1)
DATA n
A
DADR
DATA n
Write THR (Data n+1)
A
W
A
A
Write THR (Data n+x)
DATA n+5
Last data sent
DATA
Write THR (Data n+x)
DATA n+5
Last data sent
A
(ACK received and TXRDY = 1)
A
A
DATA n+x
STOP sent automaticaly
(ACK received and TXRDY = 1)
(ACK received and TXRDY = 1)
P
STOP sent automaticaly
DATA n+x
STOP sent automaticaly
Figure
6222F–ATARM–14-Jan-11
A
32-9. When the
A
P
P