SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 146

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

21.6.6
Figure 21-6. NAND Flash Signal Multiplexing on EBI Pins
146
SMC
SAM7SE512/256/32
NAND Flash Support
NWR0_NWE
NCS3
NRD
The EBI integrates circuitry that interfaces to NAND Flash devices.
The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space.
Programming the CS3A field in the Chip Select Assignment Register to the appropriate value
enables the NAND Flash logic
Access to an external NAND Flash device is then made by accessing the address space
reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF).
The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE
and NANDWE signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated
as soon as the transfer address fails to lie in the NCS3 address space. For details on these
waveforms, refer to the Static Memory Controller Section.
(1)
enabled (default state after reset) or as PIO Output set at logic level 1. The PIO cannot be used in PIO
Mode.
The address latch enable and command latch enable signals on the NAND Flash device are
driven respectively by address bits A21 and A22 of the EBI address bus. The command,
address or data words on the data bus of the NAND Flash device are distinguished by using
their address within the NCS3 address space. The chip enable (CE) signal of the device and the
ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even
when NCS3 is not selected, preventing the device from returning to standby mode.
(1)
When the NAND Flash Logic is used, NWR0/NWE/CFWE must be kept as PIO Input Mode with Pull-up
NAND Flash Logic
(See “EBI Chip Select Assignment Register” on page
NANDOE
NANDWE
MUX Logic
CS3A
CS3A
6222F–ATARM–14-Jan-11
NANDOE
NANDWE
158.).