SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 660

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

660
Version
6222D
Version
6222C
SAM7SE512/256/32
Figure 8-1 ”SAM7SE Memory
shown with EBI Chip Select 2
Section 8.1.2.1 ”Flash
Section 6. ”I/O Lines
updated.
PMC
Section 29.9.10 ”PMC Master Clock
TWI
Important changes to this datasheet include a clarification of Atmel TWI compatibility with I2C Standard. (See
Section 32.1 ”Overview”
Section 32.7 ”Master
bit field description modification etc.
Figure 32-2 ”Application Block
Figure 32-5 ”Master Mode Typical Application Block
New sections;
“Transmitting Data”. See also:
Section 32.7.6 ”Internal Address”
32.7.6.2 ”10-bit Slave Addressing”
Section 32.9.6 ”Read Write
Fixed typo in ARBLST bit fields;
Interrupt Mask Register”
Inserted EOSACC bit field description in
Comments
Overview:
Comments
“Two Wire Interface (TWI)”
the datasheet:
(32.7.7 “Using The Peripheral DMA Controller (PDC)” removed from
numbering effected.
(32.9.45 “PDC” removed from
Table 32-4, “Register
Section 32.10.6 ”TWI Status
removed.
Section 32.10.7 ”TWI Interrupt Enable
descriptions removed.
Section 32.10.8 ”TWI Interrupt Disable
descriptions removed.
Section 32.10.9 ”TWI Interrupt Mask
descriptions removed.
Section 32.7.4 ”Master Transmitter Mode”
page
Considerations”,
Mode”, rewritten. New Master Read-write flowcharts, new Read-write transfer waveforms,
353,
Overview”, updated AT91SAM7SE32 ...”reads as 8192 32-bit words.”
Mapping”, reserved offset for PDC removed
and
page
Flowcharts”, updated and new flowcharts added.
Table
Erroneous text references to PDC functionality removed from the TWI section of
Register”, TXBUFE, RXBUFF, ENDTX, ENDRX bit fields and descriptions
Mapping”, Compact Flash not shown w/EBI Chip Select 5. Compact Flash is
Figure
Diagram”, updated
page
355.
“TWI Interrupt Enable
added and includes,
See also:
32-1)
Register”, MDIV removed from bit fields 9 and 8.
368), subsequent chapter numbering effected.
32-6,
Register”,TXBUFE, RXBUFF, ENDTX, ENDRX bit fields and
“JTAG Port Pins”,“Test Pin”,“Reset Pin”,“ERASE
Register”, TXBUFE, RXBUFF, ENDTX, ENDRX bit fields and
Register”,TXBUFE, RXBUFF, ENDTX, ENDRX bit fields and
“TWI Interrupt Enable Register”
Figure
Figure
32-7,
32-11,
Diagram”, updated
Section 32.7.6.1 ”7-bit Slave Addressing”
Register”,
Figure
and
Figure 32-12
Section 32.7.5 ”Master Receiver Mode”
32-8,
“TWI Interrupt Disable Register”
Figure 32-9
page
and
357), subsequent chapter
Figure 32-13
and
Figure 32-10
Pin”; descriptions
and
and
Section
replace
“TWI
6222F–ATARM–14-Jan-11
Change
Request
Ref.
5187
Change
Request
Ref.
4804
4512
5062
4766
4373
4584
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