SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 638

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

40.8.5
These timings are given for a maximum 30 pF load on SDCK and a maximum 50 pF load on the databus.
Table 40-29. SDRAMC Clock Signal
Table 40-30. SAM7SE512/256 SDRAMC Signals
638
Symbol
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
Symbol
1/(t
t
CPSDCK
CPSDCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SAM7SE512/256/32
)
SDRAMC Signals
Parameter
SDRAM Controller Clock Frequency
SDRAM Controller Clock Period
Parameter
SDCKE High before SDCK Rising Edge
SDCKE Low after SDCK Rising Edge
SDCKE Low before SDCK Rising Edge
SDCKE High after SDCK Rising Edge
SDCS Low before SDCK Rising Edge
SDCS High after SDCK Rising Edge
RAS Low before SDCK Rising Edge
RAS High after SDCK Rising Edge
SDA10 Change before SDCK Rising Edge
SDA10 Change after SDCK Rising Edge
Address Change before SDCK Rising Edge
Address Change after SDCK Rising Edge
Bank Change before SDCK Rising Edge
Bank Change after SDCK Rising Edge
CAS Low before SDCK Rising Edge
CAS High after SDCK Rising Edge
DQM Change before SDCK Rising Edge
DQM Change after SDCK Rising Edge
D0-D15 in Setup before SDCK Rising Edge
D0-D15 in Hold after SDCK Rising Edge
D16-D31 in Setup before SDCK Rising Edge
D16-D31 in Hold after SDCK Rising Edge
SDWE Low before SDCK Rising Edge
SDWE High after SDCK Rising Edge
D0-D15 Out Valid before SDCK Rising Edge
D0-D15 Out Valid after SDCK Rising Edge
D16-D31 Out Valid before SDCK Rising Edge
D16-D31 Out Valid after SDCK Rising Edge
1.8V Supply
1.8V Supply
41.7
17.5
20.5
20.5
10.5
20.5
10.5
20.5
20.5
10.5
20.5
20.5
10.5
20.5
8.5
6.5
6.5
22
11
11
20
10
16
16
17
17
9
3
3
Min
Min
3.3V Supply
3.3V Supply
10.5
12.5
12.5
20.7
9.5
7.5
7.5
9.5
5.5
4.5
5.5
4.5
12
10
10
10
10
10
8
8
8
9
8
9
8
9
2
2
8
1.8V Supply
Supply
1.8V
24
Max
Max
3.3V Supply
3.3V Supply
6222F–ATARM–14-Jan-11
48.2
Units
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns