SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 45

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

11.2.4.1
6222F–ATARM–14-Jan-11
Modes and Exception Handling
Table 11-1.
Registers R0 to R7 are unbanked registers. This means that each of them refers to the same 32-
bit physical register in all processor modes. They are general-purpose registers, with no special
uses managed by the architecture, and can be used wherever an instruction allows a general-
purpose register to be specified.
Registers R8 to R14 are banked registers. This means that each of them depends on the current
mode of the processor.
All exceptions have banked registers for R14 and R13.
After an exception, R14 holds the return address for exception processing. This address is used
to return after the exception is processed, as well as to address the instruction that caused the
exception.
R13 is banked across exception modes to provide each exception handler with a private stack
pointer.
The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin with-
out having to save these registers.
User and
System Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
PC
CPSR
ARM7TDMI ARM Modes and Registers Layout
Supervisor
Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_SVC
R14_SVC
PC
CPSR
SPSR_SVC
Abort Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_ABORT
R14_ABORT
PC
CPSR
SPSR_ABORT
Undefined
Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_UNDEF
R14_UNDEF
PC
CPSR
SPSR_UNDEF
SAM7SE512/256/32
Interrupt
Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_IRQ
R14_IRQ
PC
CPSR
SPSR_IRQ
Mode-specific banked registers
Fast Interrupt
Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
PC
CPSR
SPSR_FIQ
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