SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 654

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

43.2.2
43.2.2.1
43.2.3
43.2.3.1
43.2.3.2
43.2.3.3
43.2.3.4
43.2.4
43.2.4.1
654
SAM7SE512/256/32
Flash Memory
Pulse Width Modulation Controller (PWM)
Real-Time Timer (RTT)
Flash: Power Consumption with data read access with multiple load of two words
PWM: Update when PWM_CCNTx = 0 or 1
PWM: Update when PWM_CPRDx = 0
PWM: Counter Start Value
PWM: Behavior of CHIDx Status Bits in the PWM_SR Register
RTT: Possible Event Loss when Reading RTT_SR
When no Wait State (FWS = 0) is programmed and when data read access is performed with a
multiple load of two words, the internal Flash may stay in read mode.
It implies a potential increase of power consumption on VDDCORE (around 2 mA). Note that it
does not concern the program execution; thus, no issue is present when the program is fetching
out of Flash.
2 workarounds are possible:
If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty
Cycle Register is directly modified when writing the Channel Update Register.
Check the Channel Counter Register before writing the Channel Update Register.
When the Channel Period Register equals 0, the period update is not operational.
Do not write 0 in the Channel Period Register.
In left aligned mode, the first start value of the counter is 0. For the other periods, the counter
starts at 1.
None.
Erratic behavior of the CHIDx status bit in the PWM_SR Register. When a channel is disabled
by writing in the PWM_DIS Register just after enabling it (before completion of a Clock Period of
the clock selected for the channel), the PWM line is internally disabled but the CHIDx status bit
in the PWM_SR stays at 1.
Do not disable a channel before completion of one period of the selected clock.
If an event (RTTINC or ALMS) occurs within the same slow clock cycle that RTT_SR is read, the
corresponding bit might be cleared. This might lead to the loss of this event.
• Add one Wait State when performing these data read accesses (FWS =1)
• After the multiple load, perform a single read data access to an address different from the
previous address accesses.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6222F–ATARM–14-Jan-11