SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 126

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

20.2.5.6
20.2.5.7
20.2.5.8
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SAM7SE512/256/32
Flash Security Bit Command
SAM7SE512 Select EFC Command
Memory Write Command
A security bit can be set using the Set Security Bit command (SSE). Once the security bit is
active, the Fast Flash programming is disabled. No other command can be run. An event on the
Erase pin can erase the security bit once the contents of the Flash have been erased.
The SAM7SE512 security bit is controlled by the EFC0. To use the Set Security Bit command,
the EFC0 must be selected using the Select EFC command.
Table 20-13. Set Security Bit Command
The commands WPx, EA, xLB, xFB are executed using the current EFC controller. The default
EFC controller is EFC0. The Select EFC command (SEFC) allows selection of the current EFC
controller.
Table 20-14. Select EFC Command
This command is used to perform a write access to any memory location.
The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking
can be chained; an internal address buffer is automatically increased.
Table 20-15. Write Command
Step
1
2
Step
1
2
Step
1
2
3
4
5
6
7
...
n
n+1
n+2
n+3
Handshake Sequence
Write handshaking
Write handshaking
Handshake Sequence
Write handshaking
Write handshaking
Handshake Sequence
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Write handshaking
...
Write handshaking
Write handshaking
Write handshaking
Write handshaking
MODE[3:0]
CMDE
ADDR0
ADDR1
ADDR2
ADDR3
DATA
DATA
...
ADDR0
ADDR1
ADDR2
ADDR3
MODE[3:0]
CMDE
DATA
MODE[3:0]
CMDE
DATA
DATA[15:0]
WRAM
32-bit Memory Address First byte
32-bit Flash Address
32-bit Flash Address
32-bit Flash Address Last Byte
*Memory Address++
*Memory Address++
...
32-bit Memory Address First byte
32-bit Flash Address
32-bit Flash Address
32-bit Flash Address Last Byte
DATA[15:0]
SSE
0
DATA[15:0]
SEFC
0 = Select EFC0
1 = Select EFC1
6222F–ATARM–14-Jan-11