SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 588

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

38.6.10
Name:
Access:
WARNING: Due to synchronization between MCK and UDPCK, the software application must wait for the end of the write
operation before executing another write by polling the bits which must be set/cleared.
588
/// Bitmap for all status bits in CSR that are not effected by a value 1.
#define REG_NO_EFFECT_1_ALL
/// Sets the specified bit(s) in the UDP_CSR register.
/// \param endpoint The endpoint number of the CSR to process.
/// \param flags The bitmap to set to 1.
#define SET_CSR(endpoint, flags) \
/// Clears the specified bit(s) in the UDP_CSR register.
/// \param endpoint The endpoint number of the CSR to process.
/// \param flags The bitmap to clear to 0.
#define CLEAR_CSR(endpoint, flags) \
EPEDS
DIR
31
23
15
–
7
{ \
}
{ \
SAM7SE512/256/32
UDP Endpoint Control and Status Register
volatile unsigned int reg; \
reg = AT91C_BASE_UDP->UDP_CSR[endpoint] ; \
reg |= REG_NO_EFFECT_1_ALL; \
reg |= (flags); \
AT91C_BASE_UDP->UDP_CSR[endpoint] = reg; \
while ( (AT91C_BASE_UDP->UDP_CSR[endpoint] & (flags)) != (flags)); \
volatile unsigned int reg; \
reg = AT91C_BASE_UDP->UDP_CSR[endpoint]; \
reg |= REG_NO_EFFECT_1_ALL; \
RX_DATA_
BK1
30
22
14
UDP_CSRx [x = 0..Y]
–
–
6
Read-write
FORCE
STALL
29
21
13
–
–
5
| AT91C_UDP_RX_DATA_BK1\
| AT91C_UDP_STALLSENT\
| AT91C_UDP_RXSETUP\
| AT91C_UDP_TXCOMP
AT91C_UDP_RX_DATA_BK0\
TXPKTRDY
28
20
12
–
–
4
RXBYTECNT
STALLSENT
ISOERROR
DTGLE
27
19
11
–
3
RXSETUP
26
18
10
2
RXBYTECNT
RX_DATA_
EPTYPE
BK0
25
17
9
1
6222F–ATARM–14-Jan-11
TXCOMP
24
16
8
0