SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 197

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

• DBW: Data Bus Width
• DRP: Data Read Protocol
0: Standard Read Protocol is used.
1: Early Read Protocol is used.
• ACSS: Address to Chip Select Setup
• RWSETUP: Read and Write Signal Setup Time
See definition and description below.
• RWHOLD: Read and Write Signal Hold Time
See definition and description below
Notes:
6222F–ATARM–14-Jan-11
0
0
0
0
1
1
1
1
1. For a visual description, please refer to
2. In Standard Read Protocol.
3. In Early Read Protocol. (It is not possible to use the parameters RWSETUP or RWHOLD in this mode.)
4. When the ECC Controller is used, RWHOLD must be programmed to 1 at least.
RWSETUP
22-46
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
and
(1)
Figure 22-47 on page
ACSS
DBW
0
1
0
1
0
1
0
1
NRD Setup
½ cycle
0 cycles
1 + ½ cycles
2 + ½ cycles
3 + ½ cycles
4 + ½ cycles
5 + ½ cycles
6 + ½ cycles
7 + ½ cycles
0
1
0
1
0
1
0
1
.
(2)
(3)
or
198.
“Setup and Hold Cycles” on page 174
NWR Setup
½ cycle
1 + ½ cycles
2 + ½ cycles
3 + ½ cycles
4 + ½ cycles
5 + ½ cycles
6 + ½ cycles
7 + ½ cycles
Data Bus Width
Reserved
16-bit
8-bit
Reserved
Chip Select Waveform
Standard, asserted at the beginning of the access and deasserted at the end.
One cycle less at the beginning and the end of the access.
Two cycles less at the beginning and the end of the access.
Three cycles less at the beginning and the end of the access.
0
0
0
0
1
1
1
1
RWHOLD
0
0
1
1
0
0
1
1
(1) (4)
and the diagrams in
0
1
0
1
0
1
0
1
SAM7SE512/256/32
NRD Hold
0
1 cycles
2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
Figure 22-45
NWR Hold
½ cycle
1 cycle
2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
and
Figure
197