SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 87

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

18. Memory Controller (MC)
18.1
18.2
Figure 18-1. Memory Controller Block Diagram
6222F–ATARM–14-Jan-11
Overview
Block Diagram
ARM7TDMI
Processor
Peripheral
Controller
DMA
The Memory Controller (MC) manages the ASB bus and controls accesses requested by the
masters, typically the ARM7TDMI processor and the Peripheral DMA Controller. It features a
simple bus arbiter, an address decoder, an abort status, a misalignment detector and an
Embedded Flash Controller. In addition, the MC contains a Memory Protection Unit (MPU) con-
sisting of 16 areas that can be protected against write and/or user accesses. Access to
peripherals can be protected in the same way.
Abort
Peripheral N
Peripheral 0
Peripheral 1
Memory Controller
Arbiter
Bus
ASB
Misalignment
Protection
Interface
Memory
Detector
Status
Abort
User
Unit
Bridge
APB
APB
Address
Decoder
Embedded
Controller
Flash
SAM7SE512/256/32
From Master
to Slave
External
Interface
Internal
Internal
Flash
RAM
Bus
87