SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 356

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 32-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 32-12. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
32.7.6.2
356
TWD
TWD
TWD
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
Three bytes internal address
Two bytes internal address
One byte internal address
S
S
S
SAM7SE512/256/32
S
S
S
10-bit Slave Addressing
DADR
DADR
DADR
DADR
DADR
DADR
W
W
W
In the figures below the following abbreviations are used:
For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and
set the other slave address bits in the internal address register (TWI_IADR). The two remaining
Internal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave
Addressing.
Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10)
1. Program IADRSZ = 1,
2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.)
3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit
• S
• Sr
• P
• W
• R
• A
• N
• DADR
• IADR
W
W
W
A
A
A
address)
IADR(23:16)
A
A
A
IADR(15:8)
IADR(7:0)
Start
Repeated Start
Stop
Write
Read
Acknowledge
Not Acknowledge
Device Address
Internal Address
IADR(23:16)
IADR(15:8)
IADR(7:0)
A
A
A
IADR(15:8)
Sr
IADR(7:0)
A
A
A
DADR
IADR(15:8)
IADR(7:0)
DATA
R
A
A
Sr
IADR(7:0)
A
A
A
A
DADR
IADR(7:0)
P
DATA
DATA
A
Sr
R
A
A
N
A
DADR
DATA
P
P
DATA
DATA
6222F–ATARM–14-Jan-11
R
N
P
A
N
A
P
P