SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 141

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

21.5
21.5.1
21.6
21.6.1
21.6.2
21.6.3
21.6.4
21.6.5
6222F–ATARM–14-Jan-11
Product Dependencies
Functional Description
I/O Lines
Bus Multiplexing
Static Memory Controller
SDRAM Controller
ECC Controller
CompactFlash Support
The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines.
The programmer must first program the PIO controller to assign the External Bus Interface pins
to their peripheral function. If I/O lines of the External Bus Interface are not used by the applica-
tion, they can be used for other purposes by the PIO Controller.
The EBI transfers data between the internal ASB Bus (handled by the Memory Controller) and
the external memories or peripheral devices. It controls the waveforms and the parameters of
the external address, data and control busses and is composed of the following elements:
The EBI offers a complete set of control signals that share the 32-bit data lines, the address
lines of up to 23 bits and the control signals through a multiplex logic operating in function of the
memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and
output control lines at a stable state while no external access is being performed. Multiplexing is
also designed to respect the data float times defined in the Memory Controllers. Furthermore,
refresh cycles of the SDRAM are executed independently by the SDRAM Controller without
delaying the other external Memory Controller accesses.
For information on the Static Memory Controller, refer to the Static Memory Controller Section.
For information on the SDRAM Controller, refer to the SDRAMC Section.
For information on the ECC Controller, refer to the ECCC Section.
The External Bus Interface integrates circuitry that interfaces to CompactFlash devices.
The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 and/or
NCS2 address space. Programming the CS4A and/or CS2A bit of the Chip Select Assignment
Register
enables this logic. Access to an external CompactFlash device is then made by accessing the
• The Static Memory Controller (SMC)
• The SDRAM Controller (SDRAMC)
• The ECC Controller (ECC)
• A chip select assignment feature that assigns an ASB address space to the external devices
• A multiplex controller circuit that shares the pins between the different Memory Controllers
• Programmable CompactFlash support logic
• Programmable NAND Flash support logic
(See “EBI Chip Select Assignment Register” on page
SAM7SE512/256/32
158.) to the appropriate value
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