MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet
MCCIRM
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MCCIRM Summary of contents
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... Freescale Semiconductor, Inc. MCCI MCCI MCCI MCCI Multichannel Communication Interface For More Information On This Product, Modular Microcontroller Family Reference Manual Go to: www.freescale.com Order this document by MCCIRM/AD Rev. 1.0 ...
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Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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Freescale Semiconductor, Inc. Multichannel Communication Interface Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of ...
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Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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Freescale Semiconductor, Inc. Reference Manual — Multichannel Communication Interface Section 1. Functional Overview . . . . . . . . . . . . . . . . . . . . 15 Section 2. Signal Descriptions ...
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Freescale Semiconductor, Inc. List of Sections Reference Manual 6 Multichannel Communication Interface — Rev. 1.0 List of Sections For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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Freescale Semiconductor, Inc. Reference Manual — Multichannel Communication Interface 1.1 1.2 1.3 1.4 2.1 2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.4 2.4.1 2.4.2 3.1 3.2 3.3 3.4 3.5 Multichannel Communication Interface — Rev. 1.0 MOTOROLA For More Information On This ...
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Freescale Semiconductor, Inc. Table of Contents 3.5.1 3.5.2 3.5.3 3.5.4 3.6 3.6.1 3.6.2 3.6.3 3.7 3.7.1 3.7.2 3.7.3 4.1 4.2 4.3 4.4 4.5 4.5.1 4.5.2 4.6 4.6.1 4.6.2 4.7 4.8 4.9 4.10 4.11 Reference Manual 8 Low-Power Stop Mode . ...
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Freescale Semiconductor, Inc. 4.12 4.12.1 4.12.2 4.12.3 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.7.1 5.7.2 5.7.3 5.7.4 5.7.5 5.7.6 5.7.7 5.7.8 5.7.9 5.7.9.1 5.7.9.2 5.7.9.3 5.7.9.4 5.7.9.5 5.7.9.6 5.7.10 5.7.10.1 5.7.10.2 Multichannel Communication Interface — Rev. 1.0 MOTOROLA For ...
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Freescale Semiconductor, Inc. Table of Contents 5.7.11 5.7.11.1 5.7.11.2 5.7.11.3 5.8 5.8.1 5.8.2 5.8.3 5.8.4 B.1 B.2 B.3 B.3.1 B.3.2 B.3.3 B.3.4 B.3.5 B.3.6 B.3.7 B.3.8 B.3.9 B.3.10 B.3.11 B.3.12 B.3.13 B.3.14 B.3.15 Reference Manual 10 Frame Detection and Synchronization ...
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Freescale Semiconductor, Inc. Reference Manual — Multichannel Communication Interface Figure 1-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 4-1 4-2 4-3 4-4 4-5 4-6 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 SCI Control Register 0 (SCCR0A and ...
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Freescale Semiconductor, Inc. List of Figures Figure 5-13 SCI Data Registers (SCDRA and SCDRB .89 A-1 A-2 A-3 A-4 B-1 B-2 B-3 B-4 B-5 B-6 B-7 ...
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Freescale Semiconductor, Inc. Reference Manual — Multichannel Communication Interface Table 1-1 2-1 2-2 3-1 3-2 3-3 4-1 4-2 4-3 4-4 5-1 5-2 5-3 5-4 5-5 A-1 A-2 A-3 Multichannel Communication Interface — Rev. 1.0 MOTOROLA For More Information On This ...
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Freescale Semiconductor, Inc. List of Tables Reference Manual 14 Multichannel Communication Interface — Rev. 1.0 List of Tables For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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Freescale Semiconductor, Inc. Reference Manual — Multichannel Communication Interface 1.1 Contents 1.2 1.3 1.4 1.2 General Information The multichannel communication interface (MCCI), a module in Motorola's family of modular microcontrollers, contains three serial interfaces: • • The SPI provides easy ...
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Freescale Semiconductor, Inc. Functional Overview A modulus-type baud rate generator provides rates from 64 baud to 524 Kbaud with a 16.78-MHz system clock. Word length of either eight or nine bits is software selectable. Optional parity generation and detection provide ...
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Freescale Semiconductor, Inc. 1.4 Memory Map The MCCI memory map consists of the global registers and the SPI and SCI control, status, and data registers, as shown in memory locations shown are offsets from the base address. For the exact ...
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Freescale Semiconductor, Inc. Functional Overview The MCCI memory map includes registers that can be accessed only when the CPU is operating at the supervisor access level and registers that can be programmed to allow supervisor access only or user access. ...
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Freescale Semiconductor, Inc. Reference Manual — Multichannel Communication Interface 2.1 Contents 2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.4 2.4.1 2.4.2 2.2 Introduction The MCCI has eight external pins. When not being used by the SPI or SCI submodules, these pins ...
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Freescale Semiconductor, Inc. Signal Descriptions 2.3 SPI Pins These four pins are associated with the SPI: MISO, MOSI, SCK, and SS. The MPAR configures each pin for either SPI function or general-purpose I/O. The MDDR assigns each pin as either ...
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Freescale Semiconductor, Inc. 2.3.1 Slave Select (SS) Assertion of SS, a bidirectional signal, selects the SPI submodule for a serial transfer when the SPI is operating in slave mode. Assertion of this signal when the SPI is operating in master ...
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Freescale Semiconductor, Inc. Signal Descriptions The MDDR and WOMC assignments are valid regardless of whether the pins are configured for SPI use or general-purpose I/O. The SCI pins and their functions are listed in Pin Name Mnemonic Transmit data Receive ...
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Freescale Semiconductor, Inc. Reference Manual — Multichannel Communication Interface 3.1 Contents 3.2 3.3 3.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.6 3.6.1 3.6.2 3.6.3 3.7 3.7.1 3.7.2 3.7.3 Multichannel Communication Interface — Rev. 1.0 MOTOROLA For More Information On This Product, ...
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Freescale Semiconductor, Inc. Configuration and Control 3.2 Introduction MCCI global registers are used by the SPI (serial peripheral interface) and both SCI (serial communications interface) interfaces. These registers are used to: • • • This section discusses the functions of ...
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Freescale Semiconductor, Inc. 3.4 System Initialization After reset, the MCCI remains in an idle state. Several registers must be initialized before serial operations begin. A general sequence guide for initialization follows. Registers, fields, and bits referred to in the summary ...
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Freescale Semiconductor, Inc. Configuration and Control 3. Serial communication interface (SCIA/SCIB) Reference Manual 26 iii. Specify 16-bit transfer (SIZE) and MSB- or LSB-first transfer mode (LSBF). iv. Select master or slave operating mode (MSTR). v. Enable or ...
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Freescale Semiconductor, Inc. 3.5 Module Configuration The MMCR contains bits and fields to: • • • 3.5.1 Low-Power Stop Mode When the STOP bit in the MMCR is set, the IMB clock signal to most of the MCCI module is ...
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Freescale Semiconductor, Inc. Configuration and Control When SUPV is set, the CPU can access MCCI registers only when operating at the supervisor privilege level. When SUPV is clear, the CPU can access all MCCI registers from the user privilege level ...
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Freescale Semiconductor, Inc. 3.5.3 MCCI Module Configuration Register The MCCI module configuration regster (MMCR) contains bits and fields for placing the MCCI in stop mode, establishing the privilege level required to access certain MCCI registers, and providing the module an ...
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Freescale Semiconductor, Inc. Configuration and Control 3.5.4 MCCI Test Register The MCCI test register (MTEST) is used only during factory testing of the MCU. 3.6 Interrupts The interrupt request level of each of the three MCCI interfaces can be programmed ...
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Freescale Semiconductor, Inc. Select a value for INTV so that each MCCI interrupt vector corresponds to one of the user-defined vectors ($40–$FF). Refer to the appropriate CPU manual for additional information on interrupt vectors. 3.6.1 SCI Interrupt Level Register The ...
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Freescale Semiconductor, Inc. Configuration and Control 3.6.2 MCCI Interrupt Vector Register The MCCI interrupt vector register (MIVR) determines which three vectors in the exception vector table are to be used for MCCI interrupts. The SPI and both SCI interfaces have ...
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Freescale Semiconductor, Inc. 3.6.3 SPI Interrupt Level Register The SPI interrupt level register (ILSPI) determines the priority level of interrupts requested by the SPI. When the interrupt-request level programmed in this field matches the interrupt-request level of one of the ...
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Freescale Semiconductor, Inc. Configuration and Control 3.7 Pin Control and General-Purpose I/O The eight pins used by the SPI and SCI subsystems have alternate functions as general-purpose I/O pins. Configuring the MCCI submodule includes programming each pin for either general-purpose ...
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Freescale Semiconductor, Inc. 3.7.1 MCCI Port Data Registers Two registers are associated with port MCCI, the MCCI general-purpose I/O port. Pins used for general-purpose I/O must be configured for that function. an output port, after configuring the pins for I/O, ...
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Freescale Semiconductor, Inc. Configuration and Control 3.7.2 MCCI Pin Assignment Register The MCCI pin assignment register (MPAR) determines which of the SPI pins (with the exception of the SCK pin) actually are used by the SPI submodule and which pins ...
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Freescale Semiconductor, Inc. 3.7.3 MCCI Data Direction Register The MCCI data direction register (MDDR) configures each pin as an input or output. The MDDR affects both serial interface function and general-purpose I/O function. During reset, all MCCI pins are configured ...
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Freescale Semiconductor, Inc. Configuration and Control Reference Manual 38 Multichannel Communication Interface — Rev. 1.0 Configuration and Control For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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Freescale Semiconductor, Inc. Reference Manual — Multichannel Communication Interface 4.1 Contents 4.2 4.3 4.4 4.5 4.5.1 4.5.2 4.6 4.6.1 4.6.2 4.7 4.8 4.9 4.10 4.11 4.12 4.12.1 4.12.2 4.12.3 Multichannel Communication Interface — Rev. 1.0 MOTOROLA For More Information On ...
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Freescale Semiconductor, Inc. SPI Submodule 4.2 Introduction The SPI submodule communicates with external peripherals and other MCUs via a synchronous serial bus. The SPI (serial peripheral interface) is fully compatible with the SPI systems found on other Motorola devices, such ...
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Freescale Semiconductor, Inc. Mnemonic BAUD CPHA CPOL LSBF MISO MODF MOSI MSTR SCK SIZE SPE SPIE SPIF WCOL WOMP 4.3 Block Diagram Figure 4-1 Multichannel Communication Interface — Rev. 1.0 MOTOROLA For More Information On This Product, Table 4-1. SPI ...
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Freescale Semiconductor, Inc. SPI Submodule INTERNAL MCU CLOCK MODULUS COUNTER SPI CLOCK (MASTER) SELECT SPI CONTROL SPI STAUS REGISTER SPI INTERRUPT REQUEST Figure 4-1. SPI Submodule Block Diagram Reference Manual 42 MSB LSB 8/16-BIT SHIFT REGISTER READ DATA BUFFER CLOCK ...
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Freescale Semiconductor, Inc. 4.4 SPI Pins The SPI uses four bidirectional pins. These pins may be configured for general-purpose I/O when not needed for the SPI. pins and their functions. Refer to additional information. Master in/slave out (MISO) Master out/slave ...
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Freescale Semiconductor, Inc. SPI Submodule 3.4 System Initialization When using the SPI in master mode, include these specific steps: 1. Write to the MMCR, MIVR, and ILSPI as outlined in 2. Write to the MPAR to assign these three pins ...
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Freescale Semiconductor, Inc. 4.5.2 Slave Mode Clearing the MSTR bit in SPCR selects slave mode operation. In slave mode, the SPI is unable to initiate serial transfers. Transfers are initiated by an external bus master. Typically, slave mode is used ...
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Freescale Semiconductor, Inc. SPI Submodule 4.6 SPI Clock Phase and Polarity Controls Two bits in the SPI control register (SPCR) determine SCK phase and polarity. The clock polarity (CPOL) bit selects clock polarity (high true or low true clock). The ...
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Freescale Semiconductor, Inc. For a master, writing to the SPDR initiates the transfer. For a slave, the falling edge of SS indicates the start of a transfer. The SCK signal remains inactive for the first half of the first SCK ...
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Freescale Semiconductor, Inc. SPI Submodule For a master, writing to the SPDR initiates the transfer. For a slave, the first edge of SCK indicates the start of a transfer. The SPI is left-shifted on the first and each succeeding odd ...
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Freescale Semiconductor, Inc. System Clock Frequency 4.8 Wired-OR Open-Drain Outputs Typically, SPI bus outputs are not open-drain unless multiple SPI masters are in the system. If needed, the WOMP bit in SPCR can be set to provide wired-OR, open-drain outputs. ...
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Freescale Semiconductor, Inc. SPI Submodule A write collision is normally a slave error because a slave has no control over when a master initiates a transfer. Since a master is in control of the transfer, software can avoid a write ...
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Freescale Semiconductor, Inc. After correcting the problems that led to the mode fault, clear MODF by reading the SPSR while MODF is set and then writing to the SPCR. Control bits SPE and MSTR may be restored to their original ...
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Freescale Semiconductor, Inc. SPI Submodule 4.12.1 SPI Control Register The SPI control register (SPCR) contains parameters for configuring the SPI. The register can be read or written at any time. Register address: $XXXX38 Bit Read: SPIE ...
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Freescale Semiconductor, Inc. CPHA — Clock Phase Bit LSBF — Least Significant Bit First SIZE — Transfer Data Size Bit BAUD — SPI Serial Clock Baud Rate Bit The SPI baud rate is selected by writing a value from 2 ...
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Freescale Semiconductor, Inc. SPI Submodule 4.12.2 SPI Status Register The SPI status register (SPSR) contains SPI status information. Only the SPI can set the bits in this register. The CPU reads the register to obtain status information. Register address: $XXXX3C ...
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Freescale Semiconductor, Inc. 4.12.3 SPI Data Register The SPI data register (SPDR) is used to transmit and receive data on the serial bus. A write to this register in the master device initiates transmission or reception of another byte or ...
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Freescale Semiconductor, Inc. SPI Submodule Reference Manual 56 Multichannel Communication Interface — Rev. 1.0 SPI Submodule For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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Freescale Semiconductor, Inc. Reference Manual — Multichannel Communication Interface 5.1 Contents 5.2 5.3 5.4 5.5 5.6 5.7 5.7.1 5.7.2 5.7.3 5.7.4 5.7.5 5.7.6 5.7.7 5.7.8 5.7.9 5.7.9.1 5.7.9.2 5.7.9.3 5.7.9.4 5.7.9.5 5.7.9.6 5.7.10 5.7.10.1 5.7.10.2 5.7.11 5.7.11.1 5.7.11.2 5.7.11.3 Multichannel ...
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Freescale Semiconductor, Inc. SCI Submodule 5.8 5.8.1 5.8.2 5.8.3 5.8.4 5.2 Introduction The SCI submodule contains two independent SCI systems. Each is a full-duplex universal asynchronous receiver transmitter (UART). This SCI system is fully compatible with SCI systems found on ...
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Freescale Semiconductor, Inc. Mnemonic LOOPS RXDA, RXDB TXDA, TXDB WOMC Multichannel Communication Interface — Rev. 1.0 MOTOROLA For More Information On This Product, Table 5-1. SCI Bit/Field Quick Reference Guide Function BR Baud rate FE Framing error flag IDLE Idle ...
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Freescale Semiconductor, Inc. SCI Submodule 5.3 SCI Pins Four unidirectional pins are associated with the SCI. When the receiver or transmitter associated with a given pin is not enabled (for instance, when the bit in the associated ...
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Freescale Semiconductor, Inc. • The SCI transmitter automatically provides a start bit as the first bit of each frame and a stop bit as the final bit. In addition, it generates a parity bit preceding the stop bit, if parity ...
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Freescale Semiconductor, Inc. SCI Submodule 5.5 Parity Checking The parity type (PT) bit in SCCR1 selects even ( odd ( parity. PT affects received and transmitted data. The parity enable (PE) bit in SCCR1 determines ...
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Freescale Semiconductor, Inc. Baud Rate 5.7 SCI Transmitter The SCI transmitter consists of a transmit serial shifter and a parallel transmit data register (TDR) located in the SCDR. The transmitter is double buffered: One byte can be loaded into the ...
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Freescale Semiconductor, Inc. SCI Submodule TRANSMITTER BAUD RATE CLOCK 10- (11) - BIT Tx SHIFT REGISTER H ( PARITY GENERATOR 15 SCCR1 (CONTROL REGISTER 1) TIE TCIE SCI Rx SCI INTERRUPT ...
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Freescale Semiconductor, Inc. 5.7.1 Initializing the Transmitter A general outline for initializing the MCCI is provided in Initialization. When using the SCI transmitter, include these specific steps: 1. Write to the MCCI global registers as outlined in 2. Read the ...
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Freescale Semiconductor, Inc. SCI Submodule 5.7.2 Status Flags and Interrupts Two status flags are associated with the SCI transmitter. These flags are read (polled) by software to tell when the corresponding condition exists. Alternately, an interrupt-enable bit can be set ...
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Freescale Semiconductor, Inc. One interrupt vector is associated with each SCI subsystem; therefore, the interrupt service routine must begin by reading the SCSR to determine which interrupt or interrupts caused the service routine to be called. Possible interrupt sources include ...
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Freescale Semiconductor, Inc. SCI Submodule If the transmitter is transmitting a character when software toggles SBK on and off, exactly one break character is produced after the current character is transmitted. If the transmitter is idle when SBK is toggled, ...
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Freescale Semiconductor, Inc. when it sees a full character time of logic 1. During a message, there must never be any gap between characters within a message because even a single bit time of idle can trigger wakeup if the ...
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Freescale Semiconductor, Inc. SCI Submodule WOMC controls TXD function regardless of whether the pin is used for SCI transmissions ( general-purpose I/O pin (TE = 0). Clearing this bit causes TXD and RXD to function ...
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Freescale Semiconductor, Inc. The input of the receive serial shifter is connected to the sampling logic of the receiver bit processor. The receiver bit processor logic drives a state machine that determines the logic level for each bit time. This ...
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Freescale Semiconductor, Inc. SCI Submodule RECEIVER BAUD RATE CLOCK RxD PIN BUFFER PARITY GENERATOR 15 SCCR1 (CONTROL REGISTER 1) 15 SCI Tx SCI INTERRUPT REQUESTS REQUEST Figure 5-2. SCI Receiver Block Diagram Reference Manual 72 16 DATA RECOVERY WAKE-UP LOGIC ...
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Freescale Semiconductor, Inc. 5.7.9 Receiver Status Flags and Interrupts Six status flags are associated with the SCI receiver. RDRF is set when a character has been received and transferred into the parallel RDR. The OR flag is set if RDRF ...
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Freescale Semiconductor, Inc. SCI Submodule 5.7.9.2 Noise Flag (NF set when the SCI receiver detects noise on a valid start bit, on any of the data bits the stop bit not set by noise ...
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Freescale Semiconductor, Inc. 5.7.9.6 Idle Line Flag (IDLE) During normal serial transmission, no idle time occurs between frames. Even when all the data bits in a frame are logic 1s, the start bit provides one bit time of logic 0 ...
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Freescale Semiconductor, Inc. SCI Submodule 5.7.10 Receiver Wakeup The receiver wakeup function allows a transmitting device to direct a transmission to a single receiver group of receivers by sending an address frame at the start of a ...
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Freescale Semiconductor, Inc. When the MSB of a frame is set, the receiver clears RWU and wakes up. The byte is received normally and is transferred to the RDR, and the RDRF flag is set. If software does not recognize ...
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Freescale Semiconductor, Inc. SCI Submodule 5.7.11.1 Start Bit Detection When the receiver is first enabled or when a stop bit is received at the end of a frame, an asynchronous search is initiated to find the leading edge of the ...
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Freescale Semiconductor, Inc. 5.7.11.3 Start Bit Recognition Examples The operation of the receiver bit processor is shown in the following figures. These examples demonstrate the search for a valid start bit and the synchronization procedure as outlined. The possibility of ...
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Freescale Semiconductor, Inc. SCI Submodule Figure 5-5 Note that the high level sensed at RT3 causes the internal noise flag to be set. Even though this figure shows improper alignment of the perceived bit-time boundaries to the actual bit-time boundaries, ...
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Freescale Semiconductor, Inc. Figure 5-7 Although this noise does not affect proper synchronization with the start bit time, it does set the internal noise flag ...
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Freescale Semiconductor, Inc. SCI Submodule Figure 5-9 return a logic level 1. However, the start bit is a special case in which the majority voting scheme does not apply. In review, at least three of the samples taken at RT1, ...
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Freescale Semiconductor, Inc. *Reads access the RDR; writes access the TDR. When initializing the SCI, set the transmitter enable (TE) and receiver enable (RE) bits in SCCR1 last. A single word write to SCCR1 can be used to initialize the ...
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Freescale Semiconductor, Inc. SCI Submodule 5.8.1 SCI Control Register 0 SCCRO contains the baud rate selection field. The baud rate must be set before the SCI is enabled. The CPU can read and write this register at any time. Register ...
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Freescale Semiconductor, Inc. 5.8.2 SCI Control Register 1 SCCR1 contains a number of SCI configuration parameters, including transmitter and receiver enable bits, interrupt enable bits, and operating mode enable bits. The CPU can read and write this register at any ...
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Freescale Semiconductor, Inc. SCI Submodule PE — Parity Enable Bit M — Mode Select Bit WAKE — Wakeup by Address Mark Bit TIE — Transmit Interrupt Enable Bit TCIE — Transmit Complete Interrupt Enable Bit RIE — Receiver Interrupt Enable ...
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Freescale Semiconductor, Inc. 5.8.3 SCI Status Register The SCSR contains flags that show SCI operating conditions. These flags are cleared either by SCI hardware read/write sequence. To clear SCI transmitter flags, read the SCSR and then write ...
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Freescale Semiconductor, Inc. SCI Submodule 0RDRF — Receive Data Register Full Flag RAF — Receiver Active Flag IDLE — Idle-Line Detected Flag Under certain conditions, the IDLE flag may be set immediately following the negation of RE (SCCR1). System designs ...
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Freescale Semiconductor, Inc. 5.8.4 SCI Data Register The SCDR contains two data registers at the same address. The RDR is a read-only register that contains data received by the SCI serial interface. The data comes into the receive serial shifter ...
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Freescale Semiconductor, Inc. SCI Submodule Reference Manual 90 Multichannel Communication Interface — Rev. 1.0 SCI Submodule For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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Freescale Semiconductor, Inc. Reference Manual — Multichannel Communication Interface Table A-1. Serial Peripheral Interface Timing Characteristics No, Characteristic Operating frequency Master Slave Cycle time 1 Master Slave 2 Slave enable lead time 3 Slave enable lag time Clock (SCK) high ...
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Freescale Semiconductor, Inc. Electrical Characteristics Figure relationships of SPI pins in master and slave modes for both values of the clock phase (CPHA) bit. The clock polarity (CPOL) bit determines the inactive state of the serial clock but has no ...
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Freescale Semiconductor, Inc. Table A-2. Key to No. Characteristic 1 Master cycle time 4 Master clock (SCK) high or low time 6 Master data setup time (inputs) 7 Master data hold time (inputs) 10 Master data valid (after SCK edge) ...
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Freescale Semiconductor, Inc. Electrical Characteristics CPOL = 0 CPOL = 1 OUTPUT Reference Manual 94 SS INPUT 13 SCK INPUT 4 4 SCK INPUT MISO MSB OUT DATA 7 6 MOSI MSB IN DATA INPUT Figure A-3. ...
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Freescale Semiconductor, Inc. Table A-3. Key to No. Characteristic 1 Slave cycle time 2 Slave enable lead time 3 Slave enable lag time 4 Slave clock (SCK) high or low time 6 Slave data setup time (inputs) 7 Slave data ...
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Freescale Semiconductor, Inc. Electrical Characteristics Reference Manual 96 Multichannel Communication Interface — Rev. 1.0 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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Freescale Semiconductor, Inc. Reference Manual — Multichannel Communication Interface B.1 Contents B.2 B.3 B.3.1 B.3.2 B.3.3 B.3.4 B.3.5 B.3.6 B.3.7 B.3.8 B.3.9 B.3.10 B.3.11 B.3.12 B.3.13 B.3.14 B.3.15 Multichannel Communication Interface — Rev. 1.0 MOTOROLA For More Information On This ...
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Freescale Semiconductor, Inc. Memory Map and Registers B.2 MCCI Memory Map Access Address 15 S $00 S $02 S $04 S $06 S/U $08 S/U $0A S/U $0C S/U $0E S/U $10–$16 S/U $18 S/U $1A S/U $1C S/U $1E ...
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Freescale Semiconductor, Inc. B.3 MCCI Registers This section summarizes the MCCI registers. B.3.1 MCCI Module Configuration Register Register address: $XXXX00 Bit Read: STOP Write: Reset Figure B-1. MCCI Module ...
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Freescale Semiconductor, Inc. Memory Map and Registers B.3.2 MCCI Test Register The MCCI test register (MTEST) is used during factory testing of the MCU. Accesses to MTEST must be made only while the MCU is in test mode. B.3.3 SCI ...
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Freescale Semiconductor, Inc. B.3.4 MCCI Interrupt Vector Register Register address: $XXXX05 Bit Read: ILSCI (SCI interrupt level register) Write: Reset Unimplemented Figure B-3. MCCI Interrupt Vector Register (MIVR) INTV[7:2] — Interrupt ...
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Freescale Semiconductor, Inc. Memory Map and Registers B.3.6 MCI Port Data Registers Register name and address: MCCI Port Data Register (PORTMC), $XXXX0C MCCI Port Pin State Register (PORTMCP), $XXXX0E Bit Read: Reserved Write: Reset: Figure ...
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Freescale Semiconductor, Inc. B.3.8 MCCI Data Direction Register Register address: $XXXX0B Bit Read: Reserved Write: Reset: Figure B-7. MCCI Data Direction Register (MDDR) These bits assign the corresponding pin, when configured for general-purpose I/ ...
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Freescale Semiconductor, Inc. Memory Map and Registers WOMP — Wired-OR Mode for SPI Pins MSTR — Master/Slave Mode Select Bit CPOL — Clock Polarity Bit CPHA — Clock Phase Bit LSBF — Least Significant Bit First SIZE — Transfer Data ...
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Freescale Semiconductor, Inc. B.3.10 SPI Status Register Register address: $XXXX3C Bit Read: SPIF WCOL 0 MODF Write: Reset Figure B-9. SPI Status Register (SPSR) SPIF — SPI Finished Flag WCOL — Write ...
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Freescale Semiconductor, Inc. Memory Map and Registers B.3.11 SPI Data Register Register address: $XXXX3E Bit Read: UPPB Write: Reset: Figure B-10. SPI Data Register (SPDR) UPPB — Upper Byte Bit In a 16-bit transfer (SIZE = ...
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Freescale Semiconductor, Inc. B.3.12 SCI Control Register 0 Register name and address: SCI Control Register 0 (SCCR0A), $XXXX18 SCI Control Register 0 (SCCR0B), $XXXX28 Bit Read: Write: Reset Unimplemented Figure B-11. ...
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Freescale Semiconductor, Inc. Memory Map and Registers B.3.13 SCI Control Register 1 Register name and address: SCI Control Register 1 (SCCR1A), $XXXX1A SCI Control Register 1 (SCCR1B), $XXXX2A Bit Read: LOOPS WOMC ILT Write: Reset: 0 ...
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Freescale Semiconductor, Inc. WAKE — Wakeup by Address Mark Bit TIE — Transmit Interrupt Enable Bit TCIE — Transmit Complete Interrupt Enable Bit RIE — Receiver Interrupt Enable Bit ILIE — Idle-Line Interrupt Enable Bit TE — Transmitter Enable Bit ...
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Freescale Semiconductor, Inc. Memory Map and Registers B.3.14 SCI Status Register Register name and address: SCI Status Register (SCSRA), $XXXX1C SCI Status Register (SCSRB), $XXXX2C Bit Read: Write: Reset Unimplemented Figure ...
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Freescale Semiconductor, Inc. FE — Framing Error Flag PF — Parity Error Flag B.3.15 SCI Data Register Register name and address: SCI Data Register (SCDRA), $XXXX1E SCI Data Register (SCDRB), $XXXX2F Bit Read ...
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Freescale Semiconductor, Inc. Memory Map and Registers Reference Manual 112 Multichannel Communication Interface — Rev. 1.0 Memory Map and Registers For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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Freescale Semiconductor, Inc. Reference Manual — Multichannel Communication Interface Access levels ...
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Freescale Semiconductor, Inc. Index CPHA ...
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Freescale Semiconductor, Inc. ILIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Freescale Semiconductor, Inc. Index Master/slave mode select (MSTR 43, 45, 52, MCCI data direction register (MDDR ...
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Freescale Semiconductor, Inc. Parity bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Freescale Semiconductor, Inc. Index Receiver (SCI ...
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Freescale Semiconductor, Inc. SCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Freescale Semiconductor, Inc. Index Status flags, SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Freescale Semiconductor, Inc. UART ...
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Freescale Semiconductor, Inc. Index Reference Manual 122 Multichannel Communication Interface — Rev. 1.0 Index For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Mfax™, Motorola Fax Back System: RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/; TOUCHTONE, 1-602-244-6609; US and Canada ONLY, 1-800-774-1848 HOME PAGE: http://motorola.com/sps/ For More Information On This Product, Go to: www.freescale.com Mfax is a trademark of Motorola, Inc. © Motorola, Inc., 1999 MCCIRM/AD ...