MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 30

• Manufacturer Part Number: MCCIRM
• Description: MCCIRM Multi-Channel Communications Interface Reference Manual
• Manufacturer: Freescale Semiconductor / Motorola

Configuration and Control
3.5.4 MCCI Test Register
3.6 Interrupts
Reference Manual
30
The MCCI test register (MTEST) is used only during factory testing of the
MCU.
The interrupt request level of each of the three MCCI interfaces can be
programmed to a value of 0 (interrupts disabled) through 7 (highest
priority). These levels are selected by the ILSCIA and ILSCIB fields in
the SCI interrupt level register (ILSCI) and the ILSPI field in the SPI
interrupt level register (ILSPI). In case two or more MCCI submodules
request an interrupt simultaneously and are assigned the same interrupt
request level, the SPI submodule is given the highest priority and SCIB
is given the lowest.
When an interrupt is requested which is at a higher level than the
interrupt mask in the CPU status register, the CPU initiates an interrupt
acknowledge cycle. During this cycle, the MCCI compares its interrupt
request level to the level recognized by the CPU. If a match occurs,
arbitration with other modules begins.
Interrupting modules present their arbitration number on the intermodule
bus (IMB), and the module with the highest number wins. The arbitration
number for the MCCI is programmed into the interrupt arbitration (IARB)
field of the MMCR. Each module should be assigned a unique arbitration
number. The reset value of the IARB field is $0, which prevents the
MCCI from arbitrating during an interrupt acknowledge cycle. The IARB
field should be initialized by system software to a value from $F (highest
priority) through $1 (lowest priority). Otherwise, the CPU identifies any
interrupts generated as spurious and takes a spurious-interrupt
exception.
If the MCCI wins the arbitration, it generates an interrupt vector that
uniquely identifies the interrupting serial interface. The six most
significant bits (MSBs) are read from the interrupt vector (INTV) field in
the MCCI interrupt vector register (MIVR). The two least significant bits
(LSBs) are assigned by the MCCI according to the interrupting serial
interface, as indicated in
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Configuration and Control
Table
Multichannel Communication Interface — Rev. 1.0
3-2.
MOTOROLA