MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 49

• Manufacturer Part Number: MCCIRM
• Description: MCCIRM Multi-Channel Communications Interface Reference Manual
• Manufacturer: Freescale Semiconductor / Motorola

4.8 Wired-OR Open-Drain Outputs
4.9 Transfer Size and Direction
4.10 Write Collision
Multichannel Communication Interface — Rev. 1.0
MOTOROLA
Typically, SPI bus outputs are not open-drain unless multiple SPI
masters are in the system. If needed, the WOMP bit in SPCR can be set
to provide wired-OR, open-drain outputs. An external pullup resistor
should be used on each output line. WOMP affects all SPI pins
regardless of whether they are assigned to the SPI or used as
general-purpose I/O.
The SIZE bit in the SPCR selects a transfer size of 8 (SIZE = 0) or 16
(SIZE = 1) bits. The LSBF bit in the SPCR determines whether serial
shifting to and from the data register begins with the LSB (LSBF = 1) or
MSB (LSBF = 0).
A write collision occurs if an attempt is made to write the SPDR while a
transfer is in progress. Since the SPDR is not double buffered in the
transmit direction, a successful write to SPDR would cause data to be
written directly into the SPI shift register. Because this would corrupt any
transfer in progress, a write collision error is generated instead. The
transfer continues undisturbed, the data that caused the error is not
written to the shifter, and the WCOL bit in SPSR is set. No SPI interrupt
is generated.
Freescale Semiconductor, Inc.
System Clock
For More Information On This Product,
Frequency
16.78 MHz
Go to: www.freescale.com
Table 4-3. Examples of SCK Frequencies
SPI Submodule
Division Ratio
Required
168
510
16
34
4
8
of SPBR
Value
255
Wired-OR Open-Drain Outputs
17
84
2
4
8
Reference Manual
Actual SCK
Frequency
SPI Submodule
4.19 MHz
2.10 MHz
1.05 MHz
493 kHz
100 kHz
33 kHz
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