MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 104

• Manufacturer Part Number: MCCIRM
• Description: MCCIRM Multi-Channel Communications Interface Reference Manual
• Manufacturer: Freescale Semiconductor / Motorola

Memory Map and Registers
Reference Manual
104
WOMP — Wired-OR Mode for SPI Pins
MSTR — Master/Slave Mode Select Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
LSBF — Least Significant Bit First
SIZE — Transfer Data Size Bit
BAUD — SPI Serial Clock Baud Rate Bit
The SPI baud rate is selected by writing a value from 2 to 255 into the
BAUD field of the SPCR of the master MCU. Giving BAUD a value of
0 or 1 disables SCK. (The disabled state is determined by CPOL). At
reset, BAUD is initialized so that SCK has a 2.1-MHz SCK frequency,
given a 16.8-MHz system clock.
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0 = Outputs have normal MOS drivers.
1 = Pins designated for output by MDDR have open-drain drivers,
0 = SPI is a slave device.
1 = SPI is system master.
0 = The inactive state value of SCK is logic level 0.
1 = The inactive state value of SCK is logic level 1.
0 = Data is captured on the leading edge of SCK and changed on
1 = Data is changed on the leading edge of SCK and captured on
0 = Serial data transfer starts with MSB.
1 = Serial data transfer starts with LSB.
0 = 8-bit data transfer
1 = 16-bit data transfer
regardless of whether the pins are used as SPI outputs or for
general-purpose I/O, and regardless of whether the SPI is
enabled.
the following edge of SCK.
the following edge of SCK.
Memory Map and Registers
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Multichannel Communication Interface — Rev. 1.0
MOTOROLA