MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 44

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MCCIRM

Manufacturer Part Number
MCCIRM
Description
MCCIRM Multi-Channel Communications Interface Reference Manual
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
SPI Submodule
Reference Manual
44
3.4 System Initialization
When using the SPI in master mode, include these specific steps:
When the SPI reaches the end of the transmission, it sets the SPIF flag
in the SPSR. If the SPIE bit in the SPCR is set, an interrupt request is
generated when SPIF is asserted. After the SPSR is read with SPIF set
and then the SPDR is read or written to, the SPIF flag is cleared
automatically.
Data transfer is synchronized with the internally generated serial clock
(SCK). Control bits CPHA and CPOL in SPCR control clock phase and
polarity. Combinations of CPHA and CPOL determine the SCK edge on
which the master MCU drives outgoing data from the MOSI pin and
latches incoming data from the MISO pin. (Refer to
and Polarity
1. Write to the MMCR, MIVR, and ILSPI as outlined in
2. Write to the MPAR to assign these three pins to the SPI: MISO,
3. Write to the MDDR to direct the data flow on SPI pins. Configure
4. Write to the SPCR to assign values for BAUD, CPHA, CPOL,
5. Enable the slave device.
6. Write appropriate data to the SPI data register to initiate the
Freescale Semiconductor, Inc.
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Initialization.
MOSI, and (optionally) SS. MISO is used for serial data input in
master mode, and MOSI is used for serial data output. Either or
both may be necessary, depending on the particular application.
SS is used to generate a mode fault in master mode. If this SPI is
the only possible master in the system, the SS pin may be used
for general-purpose I/O.
the SCK (serial clock) and MOSI pins as outputs. Configure MISO
and (optionally) SS as inputs.
SIZE, LSBF, WOMP, and SPIE. Set the MSTR bit to select master
operation. Set the SPE bit to enable the SPI.
transfer.
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Controls.)
SPI Submodule
provides general initialization procedures.
Multichannel Communication Interface — Rev. 1.0
4.6 SPI Clock Phase
3.4 System
MOTOROLA

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