MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 29

• Manufacturer Part Number: MCCIRM
• Description: MCCIRM Multi-Channel Communications Interface Reference Manual
• Manufacturer: Freescale Semiconductor / Motorola

3.5.3 MCCI Module Configuration Register
Register address: $XXXX00
Multichannel Communication Interface — Rev. 1.0
MOTOROLA
Reset:
Read:
Write:
STOP
Bit 15
0
14
0
0
Figure 3-1. MCCI Module Configuration Register (MMCR)
13
0
0
The MCCI module configuration regster (MMCR) contains bits and fields
for placing the MCCI in stop mode, establishing the privilege level
required to access certain MCCI registers, and providing the module an
interrupt arbitration number. This register can be modified only when the
CPU is operating at the supervisor privilege level.
STOP — Stop Enable Bit
MMCR[14:8] — Not Implemented
SUPV — Supervisor/User Bit
MMCR[6:4] — Not Implemented
IARB — Interrupt Arbitration Number Bit
12
0
0
SUPV defines the assignable MCCI registers as either
supervisor-only access or user access.
The value in this field is used to arbitrate for the IMB when two or more
modules generate simultaneous interrupts at the same
interrupt-request level. The IARB field should be initialized by system
software to a value from $F (highest priority) through $1 (lowest
priority). Refer to
and interrupt arbitration.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Normal MCCI clock operation
1 = MCCI clock operation stopped
0 = User access permitted to registers controlled by the SUPV bit
1 = Supervisor access only permitted to MCCI registers
11
0
0
10
0
0
Go to: www.freescale.com
Configuration and Control
9
0
0
3.6 Interrupts
8
0
0
SUPV
7
0
6
0
0
for more information on interrupts
5
0
0
4
0
0
Configuration and Control
3
0
Module Configuration
Reference Manual
2
0
IARB
1
0
Bit 0
0
29