MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 31

• Manufacturer Part Number: MCCIRM
• Description: MCCIRM Multi-Channel Communications Interface Reference Manual
• Manufacturer: Freescale Semiconductor / Motorola

3.6.1 SCI Interrupt Level Register
Register address: $XXXX04
Multichannel Communication Interface — Rev. 1.0
MOTOROLA
Reset:
Read:
Write:
Bit 15
0
0
14
0
0
13
0
ILSCIB
Figure 3-2. SCI Interrupt Level Register (ILSCI)
Select a value for INTV so that each MCCI interrupt vector corresponds
to one of the user-defined vectors ($40–$FF).
Refer to the appropriate CPU manual for additional information on
interrupt vectors.
The SCI interrupt level register (ILSCI) determines the level of interrupts
requested by each SCI. Separate fields hold the interrupt-request levels
for SCIA and SCIB. This register may be accessed only when the CPU
is operating at the supervisor privilege level.
ILSCIA and ILSCIB — Interrupt Level Bits for SCIA and SCIB
12
0
ILSCIA and ILSCIB determine the interrupt-request levels of SCIA
and SCIB interrupts, respectively. Program this field to a value from
$0 (interrupts disabled) through $7 (highest priority).
Freescale Semiconductor, Inc.
For More Information On This Product,
11
0
10
0
Go to: www.freescale.com
Configuration and Control
ILSCIA
9
0
Table 3-2. MCCI Interrupt Vectors
Interface
SCIA
SCIB
8
0
SPI
7
6
MIVR (MCCI interrupt vector register)
5
INTV[1:0]
00
01
10
4
Configuration and Control
3
Reference Manual
2
1
Interrupts
Bit 0
31