MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 32

• Manufacturer Part Number: MCCIRM
• Description: MCCIRM Multi-Channel Communications Interface Reference Manual
• Manufacturer: Freescale Semiconductor / Motorola

Configuration and Control
3.6.2 MCCI Interrupt Vector Register
Reference Manual
32
Register address: $XXXX05
Reset:
Read:
Write:
Bit 15
0
= Unimplemented
14
0
ILSCI (SCI interrupt level register)
13
0
Figure 3-3. MCCI Interrupt Vector Register (MIVR)
The MCCI interrupt vector register (MIVR) determines which three
vectors in the exception vector table are to be used for MCCI interrupts.
The SPI and both SCI interfaces have separate interrupt vectors
adjacent to one another. When initializing the MCCI, program INTV[7:2]
so that INTV[7:0] correspond to one of the user-defined vectors
($40–$FF). INTV[1:0] are determined by the serial interface causing the
interrupt.
At reset, MIVR is initialized to $0F, which corresponds to the interrupt
vector in the exception table.
INTV[7:2] — Interrupt Vector [7:2] Bits
INTV[1:0] — Interrupt Vector [1:0] Bits
12
0
High-order six bits of MCCI interrupt vector programmed by user.
Writes to INTV0 and INTV1 have no meaning or effect. Reads of
INTV0 and INTV1 return a value of 1.
Freescale Semiconductor, Inc.
For More Information On This Product,
00 = SCIA is source of interrupt.
01 = SCIB is source of interrupt.
10 = SPI is source of interrupt.
11
0
10
0
Go to: www.freescale.com
Configuration and Control
9
0
8
0
7
0
Multichannel Communication Interface — Rev. 1.0
6
0
INTV[7:2]
5
0
4
0
3
1
2
1
MOTOROLA
INTV[1:0}
1
1
Bit 0
1