MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 46

• Manufacturer Part Number: MCCIRM
• Description: MCCIRM Multi-Channel Communications Interface Reference Manual
• Manufacturer: Freescale Semiconductor / Motorola

SPI Submodule
4.6 SPI Clock Phase and Polarity Controls
4.6.1 CPHA = 0 Transfer Format
Reference Manual
46
FOR REFERENCE
SCK (CPOL = 0)
SCK (CPOL = 1)
FROM MASTER
SS TO SLAVE
SCK CYCLE #
FROM SLAVE
MOSI
MISO
Two bits in the SPI control register (SPCR) determine SCK phase and
polarity. The clock polarity (CPOL) bit selects clock polarity (high true or
low true clock). The clock phase control bit (CPHA) selects one of two
transfer formats and affects the timing of the transfer. The clock phase
and polarity should be the same for the master and slave devices. In
some cases, the phase and polarity may be changed between transfers
to allow a master device to communicate with slave devices with
different requirements. The flexibility of the SPI system allows it to be
directly interfaced to almost any existing synchronous serial peripheral.
Figure 4-2
CPHA equals 0. Two waveforms are shown for SCK: one for CPOL
equal to 0 and another for CPOL equal to 1. The diagram may be
interpreted as a master or slave timing diagram since the SCK, MISO,
and MOSI pins are directly connected between the master and the slave.
The MISO signal shown is the output from the slave and the MOSI signal
shown is the output from the master. The SS line is the chip-select input
to the slave.
MSB
Figure 4-2. CPHA = 0 SPI Transfer Format
Freescale Semiconductor, Inc.
MSB
1
For More Information On This Product,
2
is a timing diagram of an 8-bit, MSB-first SPI transfer in which
6
6
Go to: www.freescale.com
SPI Submodule
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5
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4
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Multichannel Communication Interface — Rev. 1.0
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LSB
LSB
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MOTOROLA