MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 82

• Manufacturer Part Number: MCCIRM
• Description: MCCIRM Multi-Channel Communications Interface Reference Manual
• Manufacturer: Freescale Semiconductor / Motorola

SCI Submodule
5.8 SCI Registers
Reference Manual
82
Figure 5-9
return a logic level 1. However, the start bit is a special case in which the
majority voting scheme does not apply. In review, at least three of the
samples taken at RT1, RT3, RT5, and RT7 must be low. The start bit is
detected and the RT clock is synchronized. Because RT8–RT10 were
not unanimous, NF is set.
The SCI programming model includes the MCCI global and pin control
registers and eight SCI registers. Each of the two SCI units contains two
SCI control registers, one status register, and one data register. The SCI
registers are listed in
base address.
All registers may be read or written at any time by the CPU. Rewriting
the same value to any SCI register does not disrupt operation; however,
writing a different value into an SCI register when the SCI is running may
disrupt operation. To change register values, the receiver and
transmitter should be disabled with the transmitter allowed to finish first.
The status flags in the SCSR may be cleared at any time.
^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
R
1
T
1
*
Freescale Semiconductor, Inc.
RESTART RT CLOCK
R
1
T
1
*
For More Information On This Product,
R
1
T
1
*
R
1
T
1
*
depicts the case in which the majority of RT8, RT9, and RT10
R
1
T
1
*
Go to: www.freescale.com
R
1
T
1
*
R
1
T
1
*
Figure 5-9. Start Search Example 7
SCI Submodule
R
1
T
1
*
R
1
T
1
Table
*
R
0
T
1
R
T
2
R
5-5. The addresses are offsets from the
0
T
3
Multichannel Communication Interface — Rev. 1.0
R
T
4
R
0
T
5
PERCEIVED START BIT
R
T
6
ACTUAL START BIT
R
T
7
R
T
8
1
R
0
T
9
R
1
T
1
0
R
T
1
1
R
T
1
2
R
T
1
3
R
T
4
1
R
T
1
5
R
T
1
6
*
MOTOROLA
R
T
1
R
T
2
LSB
R
T
3