MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 33

• Manufacturer Part Number: MCCIRM
• Description: MCCIRM Multi-Channel Communications Interface Reference Manual
• Manufacturer: Freescale Semiconductor / Motorola

3.6.3 SPI Interrupt Level Register
Register address: $XXXX06
Multichannel Communication Interface — Rev. 1.0
MOTOROLA
Reset:
Read:
Write:
Bit 15
0
0
14
0
0
13
0
Figure 3-4. SPI Interrupt Level Register (ILSPI)
ILSPI
The SPI interrupt level register (ILSPI) determines the priority level of
interrupts requested by the SPI. When the interrupt-request level
programmed in this field matches the interrupt-request level of one of the
SCI interfaces and both request an interrupt simultaneously, the SPI is
given priority. This register may be accessed only when the CPU is
operating at the supervisor privilege level.
ILSPI — Interrupt Level for SPI Bit
12
0
ILSPI determines the priority level of SPI interrupts. Program this field
to a value from $0 (interrupts disabled) through $7 (highest priority).
Freescale Semiconductor, Inc.
For More Information On This Product,
11
0
10
0
0
Go to: www.freescale.com
Configuration and Control
9
0
0
8
0
0
7
6
5
Reserved
4
Configuration and Control
3
Reference Manual
2
1
Interrupts
Bit 0
33