MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 75

• Manufacturer Part Number: MCCIRM
• Description: MCCIRM Multi-Channel Communications Interface Reference Manual
• Manufacturer: Freescale Semiconductor / Motorola

5.7.9.6 Idle Line Flag (IDLE)
Multichannel Communication Interface — Rev. 1.0
MOTOROLA
During normal serial transmission, no idle time occurs between frames.
Even when all the data bits in a frame are logic 1s, the start bit provides
one bit time of logic 0 during the frame. An idle line, in contrast, is a
sequence of 1s equal to the current frame size. (Frame size is
determined by the state of the M bit in SCCR1.)
The receiver hardware can detect an idle line. This function can be used
to indicate when a group of serial transmissions is finished. Idle line
detection is always enabled. When an idle line condition is detected, the
IDLE flag in SCSR is set.
The SCI receiver has both short and long idle-line detection capability.
The idle line type (ILT) bit in SCCR1 determines which type of detection
is used. For short idle-line detection, the receiver bit processor counts
contiguous logic 1 bit times whenever they occur. Short detection
provides the earliest possible recognition of an idle line condition,
because the stop bit and contiguous logic 1s before and after it are
counted. Long idle-line detection starts counting idle time only after a
valid stop bit is received. Only a complete idle frame results in the
detection of an idle line.
When idle-line receiver wakeup is used (see
long idle-line detection prevents the receiver from being awakened
prematurely if the message preceding the start of the idle line contained
1s in advance of its stop bit. (Since receiver status flags, however,
cannot be set when RWU = 1, the IDLE flag cannot be used with receiver
wakeup.)
In addition, in some applications, CPU overhead can cause a bit time of
logic level 1 to occur between frames. This bit time does not affect
content, but if it occurs after a frame of 1s when short detection is
enabled, the receiver flags an idle line.
When the idle-line interrupt enable (ILIE) bit in SCCR1 is set, an interrupt
request is generated when the IDLE flag is set. The flag is cleared by
reading the SCSR and SCDR in sequence. IDLE is not set again until
after at least one frame has been received (RDRF = 1). This prevents an
extended idle interval from causing more than one interrupt.
Freescale Semiconductor, Inc.
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SCI Submodule
5.7.10 Receiver
Reference Manual
SCI Submodule
SCI Transmitter
Wakeup),
75