MCCIRM Freescale Semiconductor / Motorola, MCCIRM Datasheet - Page 17

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MCCIRM

Manufacturer Part Number
MCCIRM
Description
MCCIRM Multi-Channel Communications Interface Reference Manual
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
1.4 Memory Map
Multichannel Communication Interface — Rev. 1.0
MOTOROLA
S = Supervisor access only
S/U = Supervisor access only or user access, depending on SUPV bit in MMCR
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S
S
S
S
Address
$10–$16
$20–$26
$30–$36
Offset
$0A
$0C
$0E
$1A
$1C
$1E
$2A
$2C
$2E
$3A
$3C
$3E
$00
$02
$04
$06
$08
$18
$28
$38
The MCCI memory map consists of the global registers and the SPI and
SCI control, status, and data registers, as shown in
memory locations shown are offsets from the base address. For the
exact location of MCCI registers in the MCU memory map, refer to the
appropriate MCU user's manual.
15
Freescale Semiconductor, Inc.
For More Information On This Product,
SCI interrupt register (ILSCI)
SPI interrupt register (ILSPI)
Table 1-1. MCCI Memory Map
Go to: www.freescale.com
Reserved
Reserved
Reserved
Reserved
Functional Overview
MCCI module configuration register (MMCR)
SCIA control register 0 (SCCR0A)
SCIA control register 1 (SCCR1A)
SCIB control register 0 (SCCR0B)
SCIB control register 1 (SCCR1B)
SCIA status register (SCSRA)
SCIB status register (SCSRB)
SCIA data register (SCDRA)
SCIB data register (SCDRB)
MCCI test register (MTEST)
SPI control register (SPCR)
SPI status register (SPSR)
SPI data register (SPDR)
Reserved
Reserved
Reserved
Reserved
8 7
MCCI port pin state register (PORTMCP)
MCCI pin assignment register (MPAR)
MCCI interrupt vector register (MIVR)
MCCI data direction register (MDDR)
MCCI port data register (PORTMC)
Reserved
Table
Functional Overview
Reference Manual
1-1. The
Memory Map
0
17

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